ICS1562B datasheet(5/20 Pages) ICST

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External Feedback Operation

The ICS1562B-201 option also supports the inclusion of an

external counter as the feedback divider of the PLL. This mode

is useful in graphic systems that must be “genlocked” to

external video sources.

When the EXTFBEN bit is set to logic 1, the phase-frequency

detector will use the EXTFBK pin as its feedback input. The

loop phase will be locked to the rising edges of the signal applied

to the EXTFBK input if the FBKPOL bit is set to logic 0.

VRAM Shift Clock Generation

The ICS1562B-201 option supports VRAM shift clock gen-

eration and interruption. By programming the N2 counter to

divide by 1, the LD/N2 output becomes a duplicate of the

LOAD output. When the SCEN bit is set, the LD/N2 output

may be synchronously started and stopped via the blank pin.

When BLANK is high, the LD/N2 will be free-running and in

phase with LOAD. When BLANK is taken low, the LD/N2

output is stopped at a low level. See Figure 5 for a diagram of

the sequence. Note that this use of the BLANK pin precludes its

use for phase comparator disable (see Line-Locked Operation).

Power-On Initialization

The ICS1562B has an internal power-on reset circuit that

performs the following functions:

Sets the multiplexer to pass the reference frequency

to the CLK+ and CLK- outputs.

Selects the modulus of the N1 divider (for the

LOAD clock) to be four.

These functions should allow initialization of most graphics

systems that cannot immediately provide for register program-

ming upon system power-up.

Because the power-on reset circuit is on the VDD supply, and

because that supply is filtered, care must be taken to allow the

reset to de-assert before programming. A safe guideline is to

allow 20 microseconds after the VDD supply reaches 4 volts.

Programming Notes

•

VCO Frequency Range: Use the post-divider to keep the

VCO frequency as high as possible within its operating

range.

•

Divider Range: For best results in normal situations (i.e,

pixel clock generation for hi-res displays), keep the refer-

ence divider modulus as short as possible (for a frequency

at the output of the reference divider in the few hundred

kHz to several MHz range). If you need to go to a lower

phase comparator reference frequency (usually required

for increased frequency accuracy), that is acceptable, but

jitter performance will suffer somewhat.

•

VCO Gain Programming: Use the minimum gain which

can reliably achieve the VCO frequency desired, as shown

on the following page:

VRAM Shift Clock Control

BLANK

LOAD

LD/N2

Figure 5

ICS1562B

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