ICS1562B datasheet(4/20 Pages) ICST

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Pipeline Delay Reset Function

The ICS1562B implements the clocking sequence required to

reset the pipeline delay on Brooktree RAMDACs when the

LOAD output is programmed for a modulus of either 3, 4, 5,

6, 8 or 10. This sequence can be generated by setting the

appropriate register bit (DACRST) to a logic 1 and then reset-

ting to logic 0.

When changing frequencies, it is advisable to allow 500 mi-

croseconds after the new frequency is selected to activate the

reset function. The output frequency of the synthesizer should

be stable enough at that point for the video DAC to correctly

execute its reset sequence. See Figure 4 for a diagram of the

pipeline delay reset sequence.

Reference Oscillator and Crystal

Selection

The ICS1562B has circuitry on-board to implement a Pierce

oscillator with the addition of only one external component, a

quartz crystal. Pierce oscillators operate the crystal in anti-

(also called parallel-) resonant mode. See the AC Charac-

teristics for the effective capacitive loading to specify when

ordering crystals.

Series-resonant crystals may also be used with the ICS1562B.

Be aware that the oscillation frequency will be slightly higher

than the frequency that is stamped on the can (typically 0.025-

0.05%).

As the entire operation of the phase-locked loop depends on

having a stable reference frequency, we recommend that the

crystal be mounted as closely as possible to the package. Avoid

routing digital signals or the ICS1562B outputs underneath or

near these traces. It is also desirable to ground the crystal can

to the ground plane, if possible.

If an external reference frequency source is to be used with the

ICS1562B. it is important that it be jitter-free. The rising and

falling edges of that signal should be fast and free of noise for

best results.

The loop phase is locked to the falling edges of the XTAL1

input signals if the REFPOL bit is set to logic 0.

Internal Feedback

The ICS1562B supports LOAD (N1) and N2 divider

chains to act as the feedback divider for the PLL.

The N1 and N2 divider chains allow a much larger modulus to

be achieved than the PLL’s own feedback divider. Additionally,

the output of the N2 counter is accessible off-chip for perform-

ing horizontal reset of the graphics system, where necessary.

This mode is set under register control (ALTLOOP bit). The

reference divider (R counter) will ordinarily be set to divide by

1 in this mode, and the reference input will be supplied to

the XTAL1 input. The output frequency of the synthesizer

will then be:

F(CLK) : = F (XTAL1) . N1 . N2.

By using the phase-detector hardware disable mode, the PLL

can be made to free-run at the beginning of the vertical interval

of the external video, and can be reactivated at its completion.

ICS1562B-001 The ICS1562B-001 supports phase detector

disable via a special control mode. When the

PDRSTEN (phase detector reset enable) bit is

set and the last address latched is 15 (0Fh), a

high level on AD3 will disable PLL locking.

ICS1562B-201 The ICS1562B-201 supports phase detector

disable via the BLANK pin. When the

PDRSTEN bit is set, a high level on the

BLANK input will disable PLL locking.

Pipeline Delay Reset Timing

STROBE

DATCLK

CLK+

LOAD

TCLK

Figure 4

ICS1562B

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