Pin Descriptions - ICS1562B-001

PIN#

NAME

DESCRIPTION

10

CLK+

Clock out (non-inverted)

9CLK

−

Clock out (inverted)

7

LOAD

Load output. This output is normally at the CLK frequency divided by N1.

2

XTAL1

Quartz crystal connection 1/external reference frequency input

3

XTAL2

Quartz crystal connection 2

1

AD0

Address/Data Bit 0 (LSB)

16

AD1

Address/Data Bit 1

15

AD2

Address/Data Bit 2

14

AD3

Address/Data Bit 3 (MSB)

8

LD/N2

Divided LOAD output. See text.

4

STROBE

Control for address/data latch

13

VDD

PLL system power (+5V. See application diagram.)

12

VDDO

Output stage power (+5V)

11

IPRG

Output stage current set

5,6

VSS

Device ground. Both pins must be connected to the same ground potential.

Pin Descriptions - ICS1562B-201

PIN#

NAME

DESCRIPTION

10

CLK+

Clock out (non-inverted)

9CLK

−

Clock out (inverted)

7

LOAD

Load output. This output is normally at the CLK frequency divided by N1.

2

XTAL1

Quartz crystal connection 1/external reference frequency input

3

XTAL2

Quartz crystal connection 2

4

DATCLK

Data Clock (Input)

16

DATA

Serial Register Data (Input)

15

HOLD~

HOLD (Input)

14

BLANK

Blanking (Input). See Text.

8

LD/N2

Divided LOAD output/shift clock. See text.

1

EXTFBK

External feedback connection for PLL (input). See text.

13

VDD

PLL system power (+5V. See application diagram.)

12

VDDO

Output stage power (+5V)

11

IPRG

Output stage current set

5,6

VSS

Device ground. Both pins must be connected.

ICS1562B

15