ADN2855

Data Sheet

Rev. B | Page 8 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SADDR[2]

RESET

SADDR[1]

NIN

PIN

VCC

VEE

SDA

VCC

VEE

DAT1P

DAT1N

NOTES

1. THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE

PACKAGE THAT MUST BE CONNECTED TO VEE (GND).

DAT2P

DAT2N

DAT3P

DAT3N

PIN 1

INDICATOR

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

ADN2855

TOP VIEW

(Not to Scale)

Figure 9. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

SADDR[2]

DI

Slave Address Bit 2.

2

RESET

DI

RESET Pulse to be Asserted Prior to Incoming Burst. Active high.

3

SADDR[1]

DI

Slave Address Bit 1.

4

NIN

AI

Differential Data Input. CML.

5

PIN

AI

Differential Data Input. CML.

6

VCC

P

3.3 V Power.

7

VEE

P

GND.

8

SDA

IO

9

SCK

DI

10

REFCLKP

DI

Differential REFCLK Input.

11

REFCLKN

DI

Differential REFCLK Input.

12

VCC

P

3.3 V Power.

13

VEE

P

GND.

14

CF2

AO

Frequency Loop Capacitor.

15

CF1

AO

Frequency Loop Capacitor.

16

DATAV

DO

Output Data Valid. LVTTL active low.

17

DAT3N

DO

Differential Deserialized Output MSB, LVDS.

18

DAT3P

DO

Differential Deserialized Output MSB, LVDS.

19

DAT2N

DO

Differential Deserialized Output Bit 2, LVDS.

20

DAT2P

DO

Differential Deserialized Output Bit 2, LVDS.

21

DAT1N

DO

Differential Deserialized Output Bit 1, LVDS.

22

DAT1P

DO

Differential Deserialized Output Bit 1, LVDS.

23

VEE

P

GND.

24

VCC

P

3.3 V Power.

25

DAT0N

DO

Differential Deserialized Output LSB, LVDS

26

DAT0P

DO

Differential Deserialized Output LSB, LVDS

27

VCC

P

3.3 V Power

28

CLKOUTP

DO

Differential Recovered Clock Output, LVDS.

29

CLKOUTN

DO

Differential Recovered Clock Output, LVDS.

30

SQUELCH

DI

Squelch Data and/or Clock Outputs. Active high.

31

VEE

P

GND

32

VCC

P

3.3 V Power.

33 (EPAD)

Exposed Pad (EPAD)

P

There is an exposed pad on the bottom of the package that must be connected to VEE (GND).