ADN2855ACPZ-R7 datasheet(13/20 Pages) AD

13 / 20 page

Data Sheet

ADN2855

Rev. B | Page 13 of 20

user exceeds the highest subaddress while reading back in

autoincrement mode, then the highest subaddress register

contents continue to be output until the master device issues a

no-acknowledge. This indicates the end of a read. In a no-

acknowledge condition, the SDATA line is not pulled low on the

ninth pulse. See Figure 11 and Figure 12 for sample write and

read data transfers and Figure 13 for a more detailed timing

diagram.

REFERENCE CLOCK

A reference clock is required to perform burst mode clock and

data recovery with the ADN2855. The reference clock must be

frequency locked to the incoming burst data. It is assumed that

the incoming burst data from the ONT is timed by a clock recov-

ered from the downstream data from the OLT and, therefore,

is inherently frequency clocked to the OLT system clock. The

reference clock can be driven differentially or single-ended. See

Figure 15 and Figure 16 for sample configurations.

The REFCLK input buffer accepts any differential signal with

a peak-to-peak differential amplitude of greater than 100 mV

(for example, LVPECL or LVDS) or a standard single-ended

low voltage TTL input, providing maximum system flexibility.

Phase noise and duty cycle of the reference clock are not critical.

REFCLKP

REFCLKN

100kΩ

BUFFER

VCC/2

Figure 15. Differential REFCLK Configuration

REFCLKP

REFCLKN

100kΩ

BUFFER

VCC/2

OUT

VCC

OSC

CLK

Figure 16. Single-Ended REFCLK Configuration

The ADN2855 must be operated in lock to reference clock

mode when in burst data recovery mode. Lock to reference

clock mode is enabled by writing a 1 to I2C Control Register

CTRLA, Bit 0. A frequency acquisition in this mode must be

initiated by writing a 1 to 0 transition to CTRLB[5].

Using the Reference Clock to Lock onto Data

In this mode, the ADN2855 locks onto a frequency derived

from the reference clock according to the following equation:

Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6]

The user must know exactly what the data rate is and provide

a reference clock that is a function of this rate. The reference

clock can be anywhere between 10 MHz and 200 MHz. By

default, the ADN2855 expects a reference clock of between

10 MHz and 25 MHz. If it is between 25 MHz and 50 MHz,

50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user

needs to configure the ADN2855 to use the correct reference

frequency range by setting two bits of the CTRLA register,

CTRLA[7:6].

Table 12. CTRLA Settings

Bit No.

Description

CTRLA[7:6]

FREF range

00 = 10 MHz to 25 MHz

01 = 25 MHz to 50 MHz

10 = 50 MHz to 100 MHz

11 = 100 MHz to 200 MHz

CTRLA[5:2]

Data rate/DIV_FREF ratio

0000 = 1

0001 = 2

…

n = 2n

…

1000 = 256

The user can specify a fixed integer multiple of the reference clock

to lock onto using CTRLA[5:2], where CTRLA should be set to

the data rate/DIV_FREF ratio, where DIV_FREF represents the

divided-down reference referred to the 10 MHz to 25 MHz band.

For example, if the reference clock frequency is 38.88 MHz and

the input data rate is 622.08 Mbps, then CTRLA[7:6] should be

set to 01 to give a divided-down reference clock of 19.44 MHz.

CTRLA[5:2] should be set to 0101, that is, 5, because

622.08 Mbps/19.44 MHz = 25

While the ADN2855 is operating in lock to reference clock mode,

if the user ever changes the reference frequency, the FREF range

(CTRLA[7:6]), or the data rate/DIV_FREF ratio (CTRLA[5:2]),

this must be followed by writing a 0 to 1 transition into the

CTRLB[5] bit to initiate a new frequency acquisition.

ADN2855ACPZ-R7 Datasheet(PDF) 13 Page - Analog Devices

ADN2855ACPZ-R7 Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL