ADN2855ACPZ-R7 datasheet(9/20 Pages) AD

Part #	ADN2855ACPZ-R7

Description	Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps Burst Mode Clock and Data Recovery IC with Deserializer

PDF	20 Pages

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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9 / 20 page

Data Sheet

ADN2855

Rev. B | Page 9 of 20

I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION

SADDR[7:1]

000

R/W

CTRL

0 = W

1 = R

Figure 10. Slave Address Configuration

S SLAVE ADDR, LSB = 0 (WR) A(S)

A(S)

DATA

SUB ADDR

A(S) P

DATA

Figure 11. I2C Write Data Transfer

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A(M) = LACK OF ACKNOWLEDGE BY MASTER

SLAVE ADDR, LSB = 0 (WR)

SLAVE ADDR, LSB = 1 (RD)

A(S)

SUB ADDR

A(S) DATA A(M)

DATA

A(M)

Figure 12. I2C Read Data Transfer

START BIT

STOP BIT

ACK

SADDR[4:0]

SLAVE ADDRESS

SUB ADDRESS

DATA

SUB ADDR[6:1]

DATA[6:1]

SCK

SDA

Figure 13. I2C Data Transfer Timing

tBUF

SDA

SCK

tLOW

tHD;STA

tHD;DAT

tSU;DAT

tHIGH

tSU;STA

tSU;STO

tHD;STA

Figure 14. I2C Port Timing Diagram

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