ADN2855ACPZ-R7 datasheet(14/20 Pages) AD

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ADN2855

Data Sheet

Rev. B | Page 14 of 20

OUTPUT MODES

Parallel or Serial Output Mode

The output of the ADN2855 can be configured in a 4-bit

parallel output nibble mode, or it can be configured in a

serial output mode. The default mode of operation is for

the Rx data to be deserialized and output in a 4-bit nibble,

present at DATxP/DATxN, where the earliest bit is present

on DAT3P/DAT3N. Setting Bit CTRLC[5] = 1 reverses the

order of the DATxP/DATxN bus such that the earliest bit is

present on DAT0P/DAT0N.

Setting bit CTRLD[7] = 1 puts the device into serial output

mode. In this mode, the Rx data is present on DAT0P/DAT0N.

Double Data Rate Mode

The default output mode for the ADN2855 is for a 4-bit deseria-

lized output with a full rate output clock, where the output

data switches on the rising edge of the output clock. When

the ADN2855 is programmed to be in parallel output mode

(CTRLD[7] = 0), setting CTRLC[4] = 1 puts the ADN2855

clock output through divide-by-two circuitry, allowing direct

interfacing to FPGAs that support data clocking on both rising

and falling edges.

When the ADN2855 is in serial output mode (deserializer off),

CTRLD[7] = 1, the default is for a half rate output clock where

the data switches on both falling and rising edges of the output

clock. Setting CTRLD[0] = 1 sets the serial clock output into full

rate mode so that the output data switches only on the rising edges

of the output clock.

RxCLK Phase Adjust

The ADN2855 provides the option of adjusting the phase of the

output clock with respect to the parallel output data. In parallel

mode, the duration of each bit is 4 UI wide, due to the deserializa-

tion. There are three additional phase adjust options other than

the baseline (that is, CLK edge in the center of the data eye): +2 UI,

+0.5 UI, and −1.5 UI. The output clock phase adjustment feature

is accessed via CTRLC[3:2]. See Table 10 for details.

DISABLE OUTPUT BUFFERS

The ADN2855 provides the option of disabling the output buffers

for power savings. The clock output buffers can be disabled by

setting CTRLD[5] = 1. For additional power savings (for example,

in a low power standby mode), the data output buffers can also

be disabled by setting CTRLD[6] = 1.

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