Data Sheet

ADN2855

Rev. B | Page 15 of 20

APPLICATIONS INFORMATION

PCB DESIGN GUIDELINES

Proper RF PCB design techniques must be used for optimal

performance.

Power Supply Connections and Ground Planes

Use of one low impedance ground plane is recommended. The

VEE pins should be soldered directly to the ground plane to

reduce series inductance. If the ground plane is an internal

plane and connections to the ground plane are made through

vias, multiple vias can be used in parallel to reduce the series

inductance. The exposed pad should be connected to the GND

plane using plugged vias so that solder does not leak through

the vias during reflow.

Use of a 10 µF electrolytic capacitor between VCC and VEE is

recommended at the location where the 3.3 V supply enters the

PCB. When using 0.1 µF and 1 nF ceramic chip capacitors, they

should be placed between the IC power supply VCC and VEE,

as close as possible to the ADN2855 VCC pins.

If connections to the supply and ground are made through vias,

the use of multiple vias in parallel helps to reduce series inductance.

Refer to the schematic in Figure 17 for recommended connections.

By using adjacent power supply and GND planes, excellent high

frequency decoupling can be realized by using close spacing

between the planes. This capacitance is given by

[ ]

A/d

C

r

PLANE

ε

88

.

0

pf =

where:

d is the separation between planes (mm).

VCO

FREQ,

LOCK

DET

PHASE

DET

PHASE

SHIFTER

LOOP

FILTER

LOOP

FILTER

DESERIALIZER

DIVIDER

DATA

RETIMING

REFCLKP,

REFCLKN

DATxP,

DATxN

CLKOUTP,

CLKOUTPN

CF1

CF2

VCC

0.1µF

0.47µF

VCC

VEE

PIN

NIN

PIN

NIN

LAOUTP

LAOUTN

RESET

SQUELCH

CML INPUT

BUFFER

2

4 × 2

2

2

0.1µF

1nF

VCC

OLT SYSTEM

CLOCK

ADN2855

OLT MAC

VCC

0.1µF

Figure 17. Typical Application Circuit