ADN2855ACPZ-R7 datasheet(10/20 Pages) AD

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ADN2855

Data Sheet

Rev. B | Page 10 of 20

Table 7. Internal Register Map1

Reg. Name

R/W

Address

CTRLA

0x08

FREF range

Data rate/DIV_FREF ratio

Lock to REFCLK

CTRLA_RD

0x05

Readback CTRLA

CTRLB

0x09

Initiate

acquisition

CTRLB_RD

0x06

Readback CTRLB

CTRLC

0x11

Bus swap

Parallel

CLKOUT mode

RxCLK phase

adjust

Output boost

CTRLD

0x22

Output

mode

Disable

data buffer

Disable clock

buffer

Serial CLKOUT

mode

All writeable registers default to 0x00.

Table 8. Control Register, CTRLA1

Bit No.

Description

[7:6]

FREF range

00 = 10 MHz to 25 MHz

01 = 25 MHz to 50 MHz

10 = 50 MHz to 100 MHz

11 = 100 MHz to 200 MHz

[5:2]

Data rate/DIV_FREF ratio

0000 = 1

0001 = 2

0010 = 4

…

n = 2n

…

1000 = 256

[1]

Set to 0

[0]

Lock to RFCLK

0 = lock to input data

1 = lock to reference clock

Where DIV_FREF is the divided down reference referred to the 10 MHz to

20 MHz band (see the Reference Clock section).

Table 9. Control Register, CTRLB

Bit No.

Description

[7:6]

Set to 0

[5]

Initiate acquisition; write a 1 followed by 0

to initiate a new acquisition

[4:0]

Set to 0

Table 10. Control Register, CTRLC

Bit No.

Description

[7:6]

Set to 0

[5]

Bus swap

0 = DAT3 is earliest bit

1 = DAT0 is earliest bit

[4]

Parallel CLKOUT mode

0 = full rate parallel clock

1 = half rate parallel clock (DDR mode)

[3:2]

RxCLK phase adjust

00 = CLK edge in center of eye

01 = +2 UI vs. baseline (CLK edge aligned with

data transition)

10 = +0.5 UI vs. baseline

11 = −1.5 UI vs. baseline

[1]

Set to 0

[0]

Output boost

0 = default

1 = boost output swing

Table 11. Control Register, CTRLD

Bit No.

Description

[7]

Output mode

0 = parallel output

1 = serial output

[6]

Disable data buffer

0 = default

1 = disable data output buffer

[5]

Disable clock buffer

0 = default

1 = disable clock output buffer

[4:1]

Set to 0

[0]

Serial CLKOUT mode

0 = half rate serial clock

1 = full rate serial clock

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