ADN2855ACPZ-R7 datasheet(12/20 Pages) AD

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ADN2855

Data Sheet

Rev. B | Page 12 of 20

FUNCTIONAL DESCRIPTION

FREQUENCY ACQUISITION

The ADN2855 operates in burst data recovery mode, which

requires the use of the OLT system reference clock as an acqui-

sition aid. The ADN2855 acquires frequency with respect to

this reference clock, which is frequency locked to the incoming

burst of data from the ONT.

The ADN2855 must be placed in lock to reference clock mode

by setting CTRLA[0] = 1. A frequency acquisition is then initiated

by writing a 1 to 0 transition into CTRLB[5]. This must be done

well before the ADN2855 is expected to lock to an incoming

burst, preferably right after power-up and once there is a valid

reference clock being supplied to the device. As long as the

reference clock to the ADN2855 is always present, this frequency

acquisition needs to take place only once. It does not need to be

repeated between bursts of data in its normal operating mode.

The initial frequency acquisition with respect to the reference

clock takes ~10 ms.

To lock to burst data, a RESET signal must be asserted following

a previous burst (or at startup) according to the timing diagrams

shown in the Reset Timing Options section. The RESET signal

must be deasserted prior to the 1010… portion of the preamble.

The ADN2855 uses a preamble detector that identifies the 1010…

portion of the preamble and quickly acquires the phase of the

incoming burst within 12 UI.

The frequency loop requires a single external capacitor between

Pin 14, CF2, and Pin 15, CF1. A 0.47 µF ± 20%, X7R ceramic

chip capacitor with <10 nA leakage current is recommended.

Leakage current of the capacitor can be calculated by dividing

the maximum voltage across the 0.47 µF capacitor, ~3 V, by the

insulation resistance of the capacitor. The insulation resistance

of the 0.47 μF capacitor should be greater than 300 MΩ.

DATAV Operation

The ADN2855 has a data valid indicator that asserts when the

ADN2855 acquires the phase of the maximum transition

density portion of the preamble. This takes 12 UI from the start

of the 1010… pattern in the preamble. The DATAV output

remains asserted until the RESET signal is asserted following

the end of the current burst of data, at which point the DATAV

output deasserts. The DATAV output is active low and is

LVTTL compatible.

SQUELCH MODE

When the squelch input, Pin 30, is driven to a TTL high state,

both the clock and data outputs are set to the zero state to

suppress downstream processing. If the squelch function is not

required, Pin 30 should be tied to VEE.

If it is desired that the DATxP/DATxN and CLKOUTP/

CLKOUN outputs be squelched while the output data is

invalid, then the DATAV pin can be hardwired directly to

the SQUELCH input.

I2C INTERFACE

The ADN2855 supports a 2-wire, I2C-compatible serial bus

driving multiple peripherals. Two inputs, serial data (SDA) and

serial clock (SCK), carry information between any devices con-

nected to the bus. Each slave device is recognized by a unique

address. The ADN2855 has four possible 7-bit slave addresses

for both read and write operations. The MSB of the 7-bit slave

address, SADDR[7] is factory programmed to 1. Bit 2 of the slave

address, SADDR[2], is set by Pin 1. Bit 1 of the slave address,

SADDR[1], is set by Pin 3. Slave Address Bits[6:3] are defaulted

to all 0s. The slave address consists of the seven MSBs of an 8-bit

word. The LSB of the word, SADDR[0], sets either a read or

write operation (see Figure 10). Logic 1 corresponds to a read

operation, and Logic 0 corresponds to a write operation.

To control the device on the bus, use the following protocol.

First, the master initiates a data transfer by establishing a start

condition, defined by a high-to-low transition on SDA while SCK

remains high. This indicates that an address/data stream

follows. All peripherals respond to the start condition and shift

the next eight bits (the 7-bit address and the R/W bit). The bits

are transferred from MSB to LSB. The peripheral that recognizes

the transmitted address responds by pulling the data line low

during the ninth clock pulse. This is known as an acknowledge

bit. All other devices withdraw from the bus at this point and

maintain an idle condition. The idle condition is where the device

monitors the SDA and SCK lines waiting for the start condition

and correct transmitted address. The R/W bit determines the

direction of the data. Logic 0 on the LSB of the first byte means

that the master writes information to the peripheral. Logic 1 on

the LSB of the first byte means that the master reads information

from the peripheral.

The ADN2855 acts as a standard slave device on the bus. The data

on the SDA pin is eight bits long supporting the 7-bit addresses

plus the R/W bit. The ADN2855 has six subaddresses to enable

the user-accessible internal registers (see Table 7 through Table

11). It, therefore, interprets the first byte as the device address

and the second byte as the starting subaddress. Autoincrement

mode is supported, allowing data to be read from or written to the

starting subaddress and each subsequent address without

manually addressing the subsequent subaddress. A data transfer

is always terminated by a stop condition. The user can also

access any unique subaddress register on a one-by-one basis

without updating all registers.

Stop and start conditions can be detected at any stage of the data

transfer. If these conditions are asserted out of sequence with

normal read and write operations, they cause an immediate

jump to the idle condition. During a given SCK high period, the

user should issue one start condition, one stop condition, or a

single stop condition followed by a single start condition. If an

invalid subaddress is issued by the user, the ADN2855 does not

issue an acknowledge, and returns to the idle condition. If the

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