MAX30002 datasheet(7/44 Pages) MAXIM

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(VDVDD = VAVDD = +1.1V to +2.0V, VOVDD = +1.65V to +3.6V, fFCLK = 32.768kHz, LN_BIOZ = 1, TA = TMIN to TMAX, unless otherwise

noted. Typical values are at VDVDD = VAVDD = +1.8V, VOVDD = +2.5V, TA = +25°C.) (Note 2)

Note 2:

All devices are 100% production tested at TA = +25ºC. Specifications over the operating temperature range and relevant

supply voltage range are guaranteed by design and characterization.

Note 3:

Guaranteed by design and characterization. Not tested in production.

Note 4:

Use this setting only for VAVDD = VDVDD ≥ 1.65V.

Note 5:

Use this setting only for VAVDD = VDVDD ≥ 1.55V.

Note 6:

Use this setting only for VAVDD = VDVDD ≥ 1.45V.

Note 7:

fSCLK = 4MHz, burst mode, BFIT[2:0] = 111, CSDO = CINTB = 50pF.

Note 8:

ESD test performed with 1kΩ series resistor designed to withstand 8kV surge voltage.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCLK Rise to CSB Fall

tCSF

Applies to 32nd RE

100

CSB Pulse-Width High

tCSPW

SDI-to-SCLK Rise Setup Time

tDS

SDI to SCLK Rise Hold Time

tDH

SCLK Fall to SDO Transition

tDOT

CLOAD = 20pF

CLOAD = 20pF, VAVDD = VDVDD ≥ 1.8V,

VDVDD ≥ 2.5V

SCLK Fall to SDO Hold

tDOH

CLOAD = 20pF

CSB Fall to SDO Fall

tDOE

Enable time, CLOAD = 20pF

CSB Rise to SDO Hi-Z

tDOZ

Disable time

FCLK Frequency

fFCLK

External reference clock

32.768

kHz

FCLK Period

tFP

30.52

µs

FCLK Pulse-Width High

tFH

50% duty cycle assumed

15.26

µs

FCLK Pulse-Width Low

tFL

50% duty cycle assumed

15.26

µs

Electrical Characteristics (continued)

MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

www.maximintegrated.com

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