MNGR_INT (0x04)

MNGR_INT is a read/write register that manages the operation of the configurable interrupt bits in response to BIOZ FIFO

conditions (see the STATUS register and BIOZ FIFO descriptions for more details).

MNGR_DYN (0x05)

MNGR_DYN is a read/write register that manages the settings of any general/dynamic modes within the device. This

register contains the interrupt thresholds for BIOZ AC Lead-Off Detection (see CNFG_GEN for more details). Unlike

many CNFG registers, changes to dynamic modes do not impact FIFO operations or require a SYNCH operation (though

the affected circuits may require time to settle, resulting in invalid/corrupted FIFO output voltage information during the

settling interval).

Table 9. MNGR_INT (0x04) Register Map

Table 10. MNGR_INT (0x04) Register Functionality

Table 11. MNGR_DYN (0x05) Register Map

REG

NAME

R/W

23/15/7

22/14/6

21/13/5

20/12/4

19/11/3

18/10/2

17/9/1

16/8/0

0x04

MNGR_

INT

R/W

x

x

x

x

x

BFIT[2:0]

x

x

x

x

x

x

x

x

x

CLR_

FAST

x

x

x

CLR_

SAMP

SAMP_IT[1:0]

INDEX

NAME

DEFAULT

FUNCTION

D[18:16]

BFIT[2:0]

011

BIOZ FIFO Interrupt Threshold (issues BINT based on number of unread

FIFO records)

000 to 111 = 1 to 8, respectively (i.e. BFIT[2:0]+1 unread records)

D[2]

CLR_SAMP

1

Sample Synchronization Pulse (SAMP) Clear Behavior:

0 = Clear SAMP on STATUS Register Read Back (recommended for debug/

evaluation only).

1 = Self-clear SAMP after approximately one-fourth of one data rate cycle.

D[1:0]

SAMP_IT[1:0]

00

Sample Synchronization Pulse (SAMP) Frequency

00 = issued every sample instant

01 = issued every 2nd sample instant

10 = issued every 4th sample instant

11 = issued every 16th sample instant

REG

NAME

R/W

23/15/7

22/14/6

21/13/5

20/12/4

19/11/3

18/10/2

17/9/1

16/8/0

0x05

MNGR_

DYN

R/W

x

x

x

x

x

x

x

x

BLOFF_HI_IT[7:0]

BLOFF_LO_IT[7:0]

MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

www.maximintegrated.com

Maxim Integrated │ 27