LT3757 datasheet(32/48 Pages) AD

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LTC7841

Rev. 0

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turn-on of the bottom MOSFET of channel 1 to be locked

to the rising edge of an external clock signal applied to

the PLLIN/MODE pin. The turn-on of channel 2’s bottom

MOSFET is thus 180 degrees out-of-phase with the exter-

nal clock. The phase detector is an edge-sensitive digi-

tal type that provides zero degrees phase shift between

the external and internal oscillators. This type of phase

detector does not exhibit false lock to harmonics of the

external clock.

If the external clock frequency is greater than the internal

oscillator’s frequency, fOSC, then current is sourced con-

tinuously from the phase detector output, pulling up the

VCO input. When the external clock frequency is less than

fOSC, current is sunk continuously, pulling down the VCO

input. If the external and internal frequencies are the same

but exhibit a phase difference, the current sources turn

on for an amount of time corresponding to the phase dif-

ference. The voltage at the VCO input is adjusted until the

phase and frequency of the internal and external oscilla-

tors are identical. At the stable operating point, the phase

detector output is high impedance and the internal filter

capacitor, CLP , holds the voltage at the VCO input.

Typically, the external clock (on the PLLIN/MODE pin)

input high threshold is 1.6V, while the input low thresh-

old is 1.2V.

Note that the LTC7841 can only be synchronized to

an external clock whose frequency is within range of

the LTC7841’s internal VCO, which is nominally 55kHz

to 1MHz. This is guaranteed to be between 75kHz

and 850kHz.

Rapid phase locking can be achieved by using the FREQ

pin to set a free-running frequency near the desired syn-

chronization frequency. The VCO’s input voltage is prebi-

ased at a frequency corresponding to the frequency set

by the FREQ pin. Once prebiased, the PLL only needs

to adjust the frequency slightly to achieve phase lock

and synchronization. Although it is not required that the

free-running frequency be near external clock frequency,

doing so will prevent the operating frequency from pass-

ing through a large range of frequencies as the PLL locks.

APPLICATIONS INFORMATION

Figure 14.

FREQ PIN RESISTOR (k)

600

800

1000

35 45 55

7841 F14

400

200

500

700

900

300

100

65 75 85 95 105 115 125

Relationship Between Oscillator

Frequency and Resistor Value at the FREQ Pin

Table 3 summarizes the different states in which the FREQ

pin can be used.

Table 3.

FREQ PIN

PLLIN/MODE PIN

FREQUENCY

DC Voltage

350kHz

INTVCC

DC Voltage

535kHz

Resistor

DC Voltage

50kHz to 900kHz

Any of the Above

External Clock

Phase Locked to

External Clock

Minimum On-Time Considerations

Minimum on-time, tON(MIN), is the smallest time duration

that the LTC7841 is capable of turning on the bottom

MOSFET. It is determined by internal timing delays and

the gate charge required to turn on the bottom MOSFET.

Low duty cycle applications may approach this minimum

on-time limit.

In forced continuous mode, if the duty cycle falls below

what can be accommodated by the minimum on-time, the

controller will begin to skip cycles but the output will con-

tinue to be regulated. More cycles will be skipped when

VIN increases. Once VIN rises above VOUT, the loop keeps

the top MOSFET continuously on. The minimum on-time

for the LTC7841 is approximately 110ns.

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