LT3757 datasheet(39/48 Pages) AD

39 / 48 page

LTC7841

Rev. 0

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Special Layout Consideration

1. Exceeding ABS Max ratings on the sense pins can result

in damage to the controller. As the Sense− pins are con-

nected directly to VLOW, it is recommended that a fast

acting diode with an appropriately high voltage rating

be used to clamp these pins to reduce voltage spiking

below ground. The diodes should be placed close to the

controller IC, with the cathode connected to SENSE1– or

SENSE2– and the anode connected to ground.

2. The TG traces from the controller IC to the gate of the

external MOSFET should be kept as short as possible

to minimize the parasitic inductance. This inductance

can cause voltage spikes that can potentially exceed

the ABS Max rating of the drivers and damage them.

A 3Ω resistor and 1nF capacitor can be used to filter

these spikes as shown in Figure 19. If the TG traces are

longer than 25mm, this filter network must be used on

both TG1 and TG2. The 1nF capacitor should be placed

as close to the TG/SW pins as possible.

Figure 19.

LTC7841

3Ω

1nF

VLOW

7841 F19

VHIGH

Filter for TG Traces > 25mm

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

to the internal oscillator and probe the actual output volt-

age. Check for proper performance over the operating

voltage and current range expected in the application.

The frequency of operation should be maintained over the

input voltage range down to dropout and until the output

load drops below the low current operation threshold—

typically 10% of the maximum designed current level in

Burst Mode operation.

The duty cycle percentage should be maintained from cycle

to cycle in a well designed, low noise PCB implementa-

tion. Variation in the duty cycle at a subharmonic rate can

suggest noise pickup at the current or voltage

sensing inputs or inadequate loop compensation.

Overcompensation of the loop can be used to tame a

poor PC layout if regulator bandwidth optimization is not

required. Only after each controller is checked for its indi-

vidual performance should both controllers be turned on

at the same time. A particularly difficult region of opera-

tion is when one controller channel is nearing its current

comparator trip point while the other channel is turning

on its bottom MOSFET. This occurs around the 50% duty

cycle on either channel due to the phasing of the internal

clocks and may cause minor duty cycle jitter.

Reduce VIN from its nominal level to verify operation with

high duty cycle. Check the operation of the undervoltage

lockout circuit by further lowering VIN while monitoring

the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling.

An embarrassing problem which can be missed in an oth-

erwise properly working switching regulator, results when

the current sensing leads are hooked up backwards. The

output voltage under this improper hook-up will still be

maintained, but the advantages of current mode control

will not be realized. Compensation of the voltage loop

will be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

APPLICATIONS INFORMATION

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