LT3757 datasheet(21/48 Pages) AD

21 / 48 page

LTC7841

Rev. 0

For more information www.analog.com

OPERATION

Device Addressing

The LTC7841 offers four different types of addressing over

the PMBus interface, specifically: 1) global, 2) device, 3)

rail addressing and 4) alert response address (ARA).

Global addressing provides a means of the PMBus master

to address all LTC7841 devices on the bus. The LTC7841

global address is fixed 0x5A or 0x5B (7 bit) or 0xB4 or

0xB6 (8 bit) and cannot be disabled.

Device addressing provides the standard means of the

PMBus master communicating with a single instance

of an LTC7841. The value of the device address is set

by the ASEL configuration pin. Rail addressing pro-

vides a means of the PMBus master addressing a set of

channels connected to the same output rail, simultane-

ously. This is similar to global addressing, however, the

PMBus address can be dynamically assigned by using

the MFR_RAIL_ADDRESS command. It is recommended

that rail addressing should be limited to command write

operations.

All four means of PMBus addressing require the user to

employ disciplined planning to avoid addressing conflicts.

Fault Status

The STATUS_WORD and ALERT pin provide fault status

information of the LTC7841 to the host.

Bus Timeout Failure

The LTC7841 implements a timeout feature to avoid hang-

ing the serial interface. The data packet timer begins at the

first START event before the device address write byte.

Data packet information must be completed within 25ms

or the LTC7841 will tri-state the bus and ignore the given

data packet. Data packet information includes the device

address byte write, command byte, repeat start event (if a

read operation), device address byte read (if a read opera-

tion), and all data bytes.

The user is encouraged to use as high a clock rate as

possible to maintain efficient data packet transfer between

all devices sharing the serial bus interface. The LTC7841

supports the full PMBus frequency range from 10kHz

to 400kHz.

Similarity Between PMBus, SMBus and I2C 2-Wire

Interface

The PMBus 2-wire interface is an incremental extension

of the SMBus. SMBus is built upon I2C with some minor

differences in timing, DC parameters and protocol. The

PMBus/SMBus protocols are more robust than simple

I2C byte commands because PMBus/SMBus provide

time-outs to prevent bus hangs and optional packet error

checking (PEC) to ensure data integrity. In general, a mas-

ter device that can be configured for I2C communication

can be used for PMBus communication with little or no

change to hardware or firmware. Repeat start (restart)

is not supported by all I2C controllers but is required for

SMBus/PMBus reads. If a general purpose I2C controller

is used, check that repeat start is supported.

For a description of the minor extensions and exceptions

PMBus makes to SMBus, refer to PMBus Specification

Part 1 Revision 1.1: Paragraph 5: Transport.

For a description of the differences between SMBus

and I2C, refer to System Management Bus (SMBus)

Specification Version 2.0: Appendix B—Differences

Between SMBus and I2C.

PMBus Serial Interface

The LTC7841 communicates with a host (master) using

the standard PMBus serial bus interface. The Timing

Diagram, Figure 1, shows the timing relationship of the

signals on the bus. The two bus lines, SDA and SCL,

must be high when the bus is not in use. External pull-up

resistors or current sources are required on these lines.

The LTC7841 is a slave device. The master can communi-

cate with the LTC7841 using the following formats:

Master transmitter, slave receiver

Master receiver, slave transmitter

The following PMBus protocols are supported:

Write Byte, Write Word, Send Byte

Read Byte, Read Word

Alert Response Address

LT3757 Datasheet(PDF) 21 Page - Analog Devices

LT3757 Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL