FEDL7022-01-06

1Semiconductor

ML7022-01

13/20

AG

Ground for the analog signal circuits.

DG

Ground for the digital signal circuits.

This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed

circuit board to make a common analog ground.

SGC

Used to generate the signal ground voltage level, by connecting a bypass capacitor. Connect a 0.1

µF capacitor

with excellent high frequency characteristics between the AG pin and the SGC pin.

During power down mode, this outputs are at the voltage level of AG with about 50 k

Ω impedance.

MCK

Master clock input.

The frequency must be 4.096 MHz.

BCLK

Shift clock signal input for the DIN and DOUT signals.

The frequency, equal to the data rate, is 256 k to 4096 kHz. This signal must be synchronized in phase with the

MCK (generated from the same clock source as MCK). Figure 1 shows the phase difference of MCK and BCLK.

RSYNC

Receive synchronizing signal input.

Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in

phase with the MCK (generated from the same clock source as MCK).

XSYNC

Transmit synchronizing signal input.

The PCM output signal from the DOUT pin is output in synchronization with this transmit synchronizing signal.

This synchronizing signal synchronizes all timing signals of all section. This signal must be synchronized in phase

with the MCK (generated from the same clock source as MCK).