FEDL7022-01-06

1Semiconductor

ML7022-01

14/20

DIN

DIN is a data input pin.

The voice band signal is converted to an analog signal in synchronization with the RSYNC signal and BCLK. The

analog signal of channel 1 is output from AOUT1 pin and the analog signal of channel 2 is output from AOUT2

pin.

The 28 bit signal structure is shown in Figure 4. It consists of voice band PCM signals (8 bits each), the general-

purpose latch signal (6 bits total), the power down control signal (1 bit per channel) and empty bits (4 bits). The

signal is shifted at a falling edge of the BCLK signal and latched into the internal register when shifted by 28 bits.

The start of the PCM data (Channel 1’s MSD) is identified at the rising edge of RSYNC.

The general purpose latch signal (C3A, C2A, C1A, C3B, C2B, C1B) are output from six latch output pins.

When the CPD1 (bit of DIN) = “0”, Channel 1 block is in a power down state. When the CPD2 (bit of DIN) = “0”,

Channel 2 block is in a power down state.

DOUT

DOUT is a data output pin.

The signal consist of a total of 28 bits containing the voice band PCM signals (each channel 8 bits), the echo bit (6

bits for latch signal and 2 bits for power down state indication), and empty bits (4 bits). The output cording format

follows ITU-T recommendation on coding law.

The output signal is output from Channel 1’s MSD bit in a sequential order, synchronizing with the rising edge of

the BCLK signal. The first bit of DOUT may be output at the rising edge of the XSYNC signal, based on the timing

between BCLK and XSYNC.

This pin is in a high impedance state during power down state.

A pull-up resistor must be connected to this pin because it is an open drain output.

Table 1 The Output Cording Format

PCMIN/PCMOUT

µ-law

INPUT/OUTPUT

Level

MSD

D2

D3

D4D5D6D7

D8

+ Full scale

1

0

0

0000

0

+0

1

1

1

1111

1

–0

0

1

1

1111

1

– Full scale

0

0

0

0000

0