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TAS2780 Datasheet(PDF) 39 Page - Texas Instruments |
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TAS2780 Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 96 page  Bit Field Type Reset Description 0 RX_EDGE RW 0h TDM RX capture clock polarity. 0b = Rising edge of SBCLK 1b = Falling edge of SBCLK 8.9.15 TDM_CFG2 (page=0x00 address=0x0A) [reset=0Ah] Bit Field Type Reset Description 7-6 IVMON_LEN[1:0] RW 0h Sets the current and voltage data to length of 00b = 16 bits 01b = 12 bits 10b = 8 bits 11b = Reserved 5-4 RX_SCFG[1:0] RW 0h TDM RX time slot select config. 00b = Mono with time slot equal to I2C address offset 01b = Mono left channel 10b = Mono right channel 11b = Stereo downmix (L+R)/2 3-2 RX_WLEN[1:0] RW 2h TDM RX word length. 00b = 16-bits 01b = 20-bits 10b = 24-bits 11b = 32-bits 1-0 RX_SLEN[1:0] RW 2h TDM RX time slot length. 00b = 16-bits 01b = 24-bits 10b = 32-bits 11b = Reserved 8.9.16 LIM_MAX_ATTN (page=0x00 address=0x0B) [reset=80h] Bit Field Type Reset Description 7-4 LIM_MAX_ATTN[3:0] RW 8h Limiter Maximum Attenuation 0h = 1 dB 1h = 2 dB 2h = 3 dB ... 0Eh = 15dB 0Fh = Reserved 3-0 Reserved R 0h Reserved 8.9.17 TDM_CFG3 (page=0x00 address=0x0C) [reset=10h] Bit Field Type Reset Description 7-4 RX_SLOT_R[3:0] RW 1h TDM RX Right Channel Time Slot. 3-0 RX_SLOT_L[3:0] RW 0h TDM RX Left Channel Time Slot. 8.9.18 TDM_CFG4 (page=0x00 address=0x0D) [reset=13h] Bit Field Type Reset Description 7 TX_KEEPCY RW 0h TDM and ICC TX SDOUT LSB data will be driven for full/half cycles when TX_KEEPEN is enabled 0b = full-cycle 1b = half-cycle 6 TX_KEEPLN RW 0h TDM and ICC TX SDOUT will hold the bus for the following when TX_KEEPEN is enabled 0b = 1 LSB cycle 1b = always 5 TX_KEEPEN RW 0h TDM and ICC TX SDOUT bus keeper enable. 0b = Disable bus keeper 1b = Enable bus keeper www.ti.com TAS2780 SLOSE75 – NOVEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TAS2780 |
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