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TAS2780 Datasheet(PDF) 24 Page - Texas Instruments

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Part # TAS2780
Description  TAS2780 Digital Input Mono Class-D Audio Amplifier With Speaker IV Sense
PDF  96 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS2780 Datasheet(HTML) 24 Page - Texas Instruments

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A hold condition (infinite or not) for a higher BOP level will not be hit if the supply ramps up faster than the lower
levels release. Specifically, whether the infinite hold for a level is hit or not depends on the release rates of the
lower levels, so even if infinite hold is set, it might not be hit.
8.4.2.9 Inter Chip Gain Alignment
The TAS2780 supports alignment of limiter and brownout prevention dynamics across devices using the
dedicated ICC (Section 8.4.2.9.1) or across the TDM output bus. This ensures consistent gain between channels
during limiting or brownout events since these dynamics are dependent on audio content, which can vary across
channels. Each device can be configured to align to a specified number of other devices, which allows creation
of groupings of devices that align only to each other.
Limiter and brownout activity is optionally transmitted by each device on SDOUT or ICC pin in an 24-bit time
slot. When both limiter and brownout are enabled the data is comprised or 11-bit limiter and 13-bit brownout
data. If only the limiter is enabled the data will be 12-bit limiter data. Gain reduction should be transmitted in
adjacent time slots for all devices that are to be aligned beginning with the first slot that is specified by the
ICGA_SLOT[5:0] register bits. The order of the devices is not important as long as they are adjacent. The time
slot for limiter gain reduction is configured by the GAIN_SLOT[5:0] register bits and enabled by the GAIN_TX
register bit being set high. The ICGA_SEN[7:0] register bits specify which time slots should be listened to for
gain alignment. This allows any number of devices between two and eight to be grouped together. At least two of
these devices should be enabled for alignment to take place.
To enable the inter-chip limiter alignment the ICLA_EN register bit should be set to high. To enable the inter chip
BOP alignment the ICBA_EN register bit should be set to high. All devices should be configured with identical
limiter and brownout prevention settings.
8.4.2.9.1 Inter-Chip Communication (ICC) Pin
The TAS2780 has a dedicated ICC bus pin that enables gain alignment (ICGA) without consuming slots on the
TDM (Section 8.4.1). The ICC pin is connected to all TAS2780 devices in the system and slots are configured
using register bits GAIN_SLOT[5:0]. This bus uses the TDM (Section 8.4.1) BCLK and FSYNC inputs and
requires all devices to be configured using the same sampling clock. The ICC pin supports separate bus keeper
configuration from the SDOUT pin on the TDM bus. If the ICC pin is disabled or used for GPIO functionality the
ICGA (Section 8.4.2.9) will occur on the TDM bus instead of the ICC pin. Register bits ICC_MODE[2:0] are used
to set the ICC pin functionality.
8.4.2.10 Class-D Settings
8.4.2.10.1 Synchronization
The TAS2780 Class-D amplifier supports spread spectrum PWM modulation, which can be enabled by setting
the AMP_SS register bit high. This can help reduce EMI in the system.
By default the Class-D amplifier switching frequency is based on the device trimmed internal oscillator. To
synchronize switching to the audio sample rate, set the CLASSD_SYNC register bit high. When the Class-D is
synchronized to the audio sample rate, the RAMP_RATE register bit must be set depending on the audio sample
rate based on either 44.1 kHz or 48 kHz frequency. For 44.1, 88.2 and 176.4 kHz, set RAMP_RATE bit high and
for 48, 96 and 192 kHz, set this bit low. This ensures that the internal ramp generator has the appropriate slope.
8.4.3 SAR ADC
A SAR ADC monitors PVDD voltage, VBAT1S voltage and die temperature. The results of these conversions are
available via register readback (PVDD_CNV[11:0], VBAT1S_CNV[11:0] and TMP_CNV[7:0] register bits). PVDD
and VBAT1S voltage conversions are also used by the limiter and brown out prevention blocks.
By default, when BOP_SRC=1 , VBAT1S conversion is enabled along with PVDD and temperature.
The ADC runs at a fixed 192 kHz sample rate with a conversion time of 5.2 µs.
Sampling rate for temperature is 10K samples/sec.
TAS2780
SLOSE75 – NOVEMBER 2021
www.ti.com
24
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Product Folder Links: TAS2780



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