| Electronic Components Datasheet Search |
|
TAS2780 Datasheet(PDF) 20 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TAS2780 Datasheet(HTML) 20 Page - Texas Instruments |
|
20 / 96 page ![]() Figure 8-4. Low Voltage Signaling The LVS fixed thresholds, when CDS_MODE[1:0]=11 (PWR_MODE2 from Section 11.1), can be set using register bits LVS_FTH_LOW[1:0]. When CDS_MODE[1:0]=00 (PWR_MODE1 from Section 11.1) the thresholds should be set with register bits LVS_FTH[4:0]. Below equations show the maximum level of the input signal in order to keep LVS below threshold (Class D switching on VBAT1S). For absolute threshold: . Input (dBFS) < LVS_FTH + (21 dBV - ChannelGain [dBV]) (1) For relative threshold: . Input (dBFS) < 20log[(VBAT1S*CD_EFF - LVS_RTH)/16] + (21 dBV - ChannelGain [dBV]) - 1.5dB (2) Where: * ChannelGain = AMP_LEVEL + DVC_LVL + SAFE_MODE (if enabled, it is -18dB). * CD_EFF is set by registers 48h-4Bh from page 0x04 and LVH_RTH is set by bits [3:0] of register 6Ah from page 0x00. * 1.5dB is an inflection factor, already included for absolute threshold. BOP, Limiter, Thermal Foldback and Thermal Gradient Gain Attenuation should not be taken into account for calculating LV_EN threshold. 8.4.2.6 Y-Bridge The TAS2780 Class-D output uses a Y-Bridge configuration to improve efficiency during playback. The LVS (Section 8.4.2.5) is internally used to select between the PVDD and VBAT1S supplies. This feature is enabled by setting CDS_MODE[1:0] bits to 2'b00 when both PVDD and VBAT1S are supplied to the device. If not configured to Y-bridge mode the device will use only the selected supply for class-D output even if clipping would otherwise occur. The device can operate using only PVDD to supply class-D output. In this configuration the VBAT1S can be provided from external supply (register bit VBAT1S=0) or generated by an internal LDO (register bit VBAT1S=1). In this case CDS_MODE[1:0] bits should be set to 2'b10. The TAS2780 Y-Bridge with Low Power on VBAT1S can be used to switch to the VBAT1S rail only at very low power when close to idle. This will reduce the class-D output swing when near idle and limit the current requirements of the VBAT1S supply. Set the CDS_MODE[1:0] register to 2'b11 for this mode. See Section 11.1 for details on programming the power mode of operation. TAS2780 SLOSE75 – NOVEMBER 2021 www.ti.com 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TAS2780 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |