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TAS2780 Datasheet(PDF) 21 Page - Texas Instruments

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Part # TAS2780
Description  TAS2780 Digital Input Mono Class-D Audio Amplifier With Speaker IV Sense
PDF  96 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS2780 Datasheet(HTML) 21 Page - Texas Instruments

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The change to the class-D supply (VBAT1S to PVDD) determined by the Section 8.4.2.5 has a delay with
respect to input signal crossing threshold and is programed by CDS_DLY[1:0] register bits.
When in Y-Bridge mode, if the PVDD falls below (VBAT1S+2.5V) level the Y-bridge will stop switching between
supplies and will remain on the PVDD supply.
8.4.2.7 Noise Gate
The TAS2780 has a noise-gate feature that monitors the input signal and powers down the class-D when the
signal goes below the set threshold set by NG_LVL[1:0] bits for longer than the time set by NG_HYST[1:0]
register bits. When the signal goes above the threshold the class-D will re-power in 7 samples before the
samples applied to the audio input interface reach the class-D bridge. This feature is enabled by setting NG_EN
bit to high. Once enabled it is able to power up and down the channel within the device processing delay
requiring no additional external control. Volume ramping can be also used during noise gate operations by
setting NG_DVR_EN bit to low.
The noise gate can be configured with finer resolution at the expense of additional I2C writes. Use NGFR_EN bit
to enable this mode and register bits NGFR_LVL[31:0] to set the fine resolution. The fine resolution hysteresis is
set using NGFR_HYST[18:3] register bits.
8.4.2.8 Supply Tracking Limiter with Brown Out Prevention
The TAS2780 contains a supply tracking limiter to control distortion and brownout prevention to mitigate
brownout events. The gain reduction that occurs due to this block can be aligned across multiple devices
using the Inter Chip Gain Alignment (ICGA) (Section 8.4.2.9) feature. The maximum device attenuation set by
DEV_MAX_ATTN[6:0] register bits can be used to limit the combination of the limiter and brownout attenuation
or the Inter-Chip Gain Aligment (ICC ) (Section 8.4.2.9).
The Supply Tracking Limiter (STL) (Section 8.4.2.8.1) and the Brownout Prevention (BOP) (Section 8.4.2.8.2)
are configured independently. The ICC, if enabled, keeps multiple device gains in sync if the STL and BOP need
to reduce the gain. However, the BOP will take priority in the device. In order to prevent the STL and BOP from
both making simultaneous adjustments to the system, the STL and ICGA will be paused once the BOP engages
until it fully releases.
The attenuation applied to the device can be selected to be either the sum of the limiter attenuation (ICLA) and
Brownout attenuation (ICBA) or the maximum of the two of them by setting the ICG_MODE register bit.
8.4.2.8.1 Supply Tracking Limiter
The TAS2780 monitors PVDD supply voltage and the audio signal to automatically decrease gain when the
audio signal peaks exceed a programmable threshold. This helps prevent clipping and extends playback time
through end of charge battery conditions. The limiter threshold can be configured to track PVDD below a
programmable inflection point with a programmable slope. A minimum threshold sets the limit of threshold
reduction from PVDD tracking.
The limiter is enabled by setting the LIM_EN bit register to high.
Configurable attack rate, hold time and release rate are provided to shape the dynamic response of the limiter
(LIM_ATK_RT[3:0], LIM_HLD_TM[2:0] and LIM_RLS_RT [3:0] register bits).
A maximum level of attenuation applied by the limiter is configurable via the LIM_MAX_ATTN[3:0] register bits. If
the limiter mode is attacking and if it reaches the maximum attenuation, gain will not be reduced any further.
The limiter begins reducing gain when the output signal level is greater than the limiter threshold. The limiter
can be configured to track PVDD below a programmable inflection point with a minimum threshold value. Figure
8-5 below shows the limiter configured to limit to a constant level regardless of PVDD level. To achieve this
behavior, set the limiter maximum threshold to the desired level via the LIM_TH_MAX[31:0] register bits. Set the
limiter inflection point (register bits LIM_INF_PT[31:0]) below the minimum allowable PVDD setting. The limiter
minimum threshold, set by register bits LIM_TH_MIN[31:0], does not impact limiter behavior in this use case.
www.ti.com
TAS2780
SLOSE75 – NOVEMBER 2021
Copyright © 2021 Texas Instruments Incorporated
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