AM79C850KC datasheet(29/97 Pages) AMD

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AMD

SUPERNET 3

(if transmitting), releases the token, and no further

transmissions can occur until the pin is deasserted.

During the time that the TRANSMIT INHIBIT function is

enabled the network timers and state machines

operate normally.

As a result of the change to the FLXI pin, which of the

two functions is selected depends upon the state of FLXI

bits, as follows:

FLXI

FLXI1

FLXI0

Function Implemented

Normal Operation

FLUSH received frame

Normal Operation

INHIBIT transmission

Reserved

Upon reset, the FLXI1:0 bits would read all zeros.

Single Frame Receive Mode

The Single Frame Receive Mode function has been

removed from the SUPERNET 3. All associated status,

modes and commands are deleted and replaced with

reserved. This causes the following changes:

1. Status Register 2 Upper:

The ‘Receive Frame’ (SRCVFRM) bit 10 and

‘Receive Frame Counter Overflow’ (SRFRCTOV) bit

9 are now reserved and return a value of zero when

read.

2. Command Register 2:

The ‘Enable Receive Single Frame’ command

(0x40) is no longer a valid command. This is now

reserved.

3. Mode Register 1:

The ‘Single-Frame Receive Mode’ bit [15] is no

longer valid. It is now a reserved bit and shall return a

value of zero when read.

Receive Queue Operation

SUPERNET 3 provides a new feature where the user

can configure the buffer memory for incoming valid

frame into two separate receive queues. The type of

frames that each queue would receive is selected in a

separate register, the Frame Selection Register

(FRSELREG). To enable two receive queues operation,

MENDRCV bit in Mode Register 3 (MDREG3) needs to

be set. If this bit is cleared, which is the case at the time

of reset, then SUPERNET 3 behaves like F+ (i.e only

one receive queue is supported, and SUPERNET 3

defaults to Receive Queue 1). If MDREG3 bit 11,

MENDRCV and both RECVX3:0 in Frame Selection

then the SUPERNET 3 would behave like FORMAC+

and the second queue is ignored. However, if one of the

RECVX3:0 bits in FRSELREG are programmed to be

“0000” then the corresponding queue would receive all

frames except the frame type selected for the other

queue. Only the second receive queue (i.e. RECV2) can

be programmed to be “0000”. Programming the RECV1

bits in the Frame Selection Register (FRSELREG) with

“0000” and RECV2 bits with a non-zero selection, will

result in no data being written in the RECV1 queue. Only

the frame type selected by RECV2 bits will be received

in the second queue.

AM79C850KC Datasheet(PDF) 29 Page - Advanced Micro Devices

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