AM79C850KC datasheet(15/97 Pages) AMD

15 / 97 page

P R E L I M I N A R Y

AMD

SUPERNET 3

word and the descriptor word at the end of the frame. In

transmit mode, when BDTAG = 0, it indicates that the

information on the BD bus is data, i.e., end-of-frame not

yet reached.

CSO

Chip-Select Output (TTL output, high impedance,

active low)

The chip-select output (active low) is a select signal for

buffer memory read and write operations. This line is in

the high-impedance state when buffer memory control

is released to the NP.

Buffer Memory Read (TTL output, high

impedance, active low)

This output signal (active low) controls the buffer

memory during a buffer-memory read accesses. This

line is in the high-impedance state when buffer memory

control is released to the NP.

Buffer Memory Write (TTL output, high

impedance, active low)

This (active low) output signal, in its active-low state,

allows write accesses to buffer memory. This line is in

the high-impedance state when buffer memory control

is released to the NP.

Host/Buffer Memory Interface (10 Pins)

All these signals are synchronous to BMCLK.

HSACK

Host Acknowledge (TTL output, high impedance)

This signal indicates that the current host read/write

request is being granted by SUPERNET 3 and allows

read/write accesses of buffer memory by the host.

HSREQ2–0

Host Request Bus (TTL input)

The host request bus specifies to SUPERNET 3 the type

of buffer memory access the host requires, as described

in the following table.

Special-frame write requests are used to set up claim,

beacon, and auto-void frames in the buffer memory (see

the discussion under Buffer Memory Operation in

SUPERNET 2 data book). These requests make use of

the WPXSF register to set up special frames in the

special-frame area.

Read request is used to retrieve received frames from

buffer memory and store them in the system memory.

Write requests are used to set up frames in buffer

memory for transmission.

HSREQ2

HSREQ1

HSREQ0

Type of Request

None.

Read Request:

Second Receive

Queue*

Special Frame

Write Request.

Read Request:

Receive Queue.

Write Request:

Synchronous Queue.

Write Request:

Asynchronous

Queue 0.

Write Request:

Asynchronous

Queue 1.

Write Request

Asynchronous

Queue 1.

Note: * Only if two receive queue operation is selected

through MDREG3.

QCTRL2–0

Buffer Queue Control (TTL output, high

impedance)

The QCTRL2–0 status output lines are encoded as de-

scribed in the following table.

AM79C850KC Datasheet(PDF) 15 Page - Advanced Micro Devices

AM79C850KC Datasheet(HTML) 15 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

Datasheet Download

Link URL