AM79C850KC datasheet(63/97 Pages) AMD

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P R E L I M I N A R Y

AMD

SUPERNET 3

BIST Pattern Requirements

This section presents the pattern requirements that the

BIST implementation should try to meet. The implemen-

tation should try to meet as many of the requirements as

possible, however, overhead considerations may make

this goal unattainable. In the case that the requirements

are not met, a means of applying these patterns

functionally must be found. The functional application of

patterns may dictate additional testability requirements

in the AF. The pattern requirements are divided into two

sections, the first deals with the testing of the portion of

the AF that is SRAM-like, the second deals with the

testing of the remaining AF logic such as the match

logic, priority encoder, exact logic, etc.

Pattern requirements for the SRAM-like portion of

the AF

The following pattern requirements are taken from a

paper by Jain and Stroud. Some of the requirements

may be architecture specific and may not be necessary.

Additional requirements may be necessary depending

on the architecture of the AF. This paper describes two

algorithms that may be used in the implementation of

the BIST test.

1. Each cell must undergo a 0_1 transition and then a

1_0 transition or vice versa. Each cell must be read

after each transition.

2. For every pair of physically adjacent cell i and j the

test writes cell i with and 1 and cell j with a 0 and then

cell i with a 0 and cell j with a 1. It then reads after

each write. To consider coupling faults between

master/slave bits, cells i and j are written with the

same data.

3. Each cell must be read twice after writing a 1 and a 0.

4. Decoder faults should be detected by writing unique

data in every memory word and then reading the AF.

5. A special sequence of data patterns should be

written and read to detect stuck-at faults in the read

column decoder logic.

6. Some memory words should be written and read

with data having different logic values on every pair

of adjacent input data lines.

Pattern requirements for the non-SRAM portion of

the AF

The following pattern requirements may be difficult to

implement in silicon and may have to be applied func-

tionally. Some of the patterns described in this section

can be applied at the same time as the SRAM tests are

being applied. The non-SRAM portion of the AF consists

of the comparator, the source address exact/inexact

match logic, the destination exact/inexact match logic,

and the multiple match logic (which includes the priority

encoder logic). The stuck-at fault model is the only fault

model used in developing the pattern requirements for

this portion of the AF. The other fault models discussed

earlier were developed for memory arrays and it would

not make sense to try to apply them to this section of

the AF.

Comparator

The output of the comparator logic is the 32 match lines

for each AF entry. The output of the comparator is

further modified by the state of the personality bits. The

comparator can be viewed as 32 48-bit wide com-

parators with one half of the inputs to each comparator

supplied by the corresponding mask and data bits for

each comparator, and the other half of the inputs to each

comparator supplied by the comparand register. For the

purpose of describing the data patterns necessary to

test each comparator it will be assumed that all valid bits

are set, all skip bits are reset and that either the SA or

DA bits are set to allow a match operation to be visible

outside the AF. The following table summarizes the truth

table for a single bit of the comparator:

Table 1. Truth Table for the Comparator

MASK

DATA

COMP

MATCH

YES

100

YES

101

110

111

YES

AM79C850KC Datasheet(PDF) 63 Page - Advanced Micro Devices

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