Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

TAS5828M Datasheet(PDF) 63 Page - Texas Instruments

Click here to check the latest version.
Part # TAS5828M
Description  TAS5828M 50-W Stereo, Digital Input, High Efficiency Closed-Loop Class-D Amplifier with Hybrid-Pro Algorithm
PDF  97 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS5828M Datasheet(HTML) 63 Page - Texas Instruments

Back Button TAS5828M Datasheet HTML 59Page - Texas Instruments TAS5828M Datasheet HTML 60Page - Texas Instruments TAS5828M Datasheet HTML 61Page - Texas Instruments TAS5828M Datasheet HTML 62Page - Texas Instruments TAS5828M Datasheet HTML 63Page - Texas Instruments TAS5828M Datasheet HTML 64Page - Texas Instruments TAS5828M Datasheet HTML 65Page - Texas Instruments TAS5828M Datasheet HTML 66Page - Texas Instruments TAS5828M Datasheet HTML 67Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 63 / 97 page
background image
Figure 8-37. ANA_CTRL Register
7
6
5
4
3
2
1
0
AMUTE_DLY
R/W
Table 8-33. ANA_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6-5
Class D bandwidth control R/W
00
00: 100kHz
01: 80kHz
10: 120kHz
11:175kHz
With Fsw=384kHz, 100kHz bandwidth is selected for high audio
performance. With Fsw=768kHz, 175kHz bandwidth should be
selected for high audio performance.
4-1
RESERVED
R/W
0000
These bits are reserved
0
L and R PWM output
phase control
R/W
0
0: out of phase
1: in phase
8.6.1.25 AGAIN Register (Offset = 54h) [reset = 0x00]
AGAIN is shown in Figure 8-38 and described in Table 8-34.
Return to Table 8-8.
Figure 8-38. AGAIN Register
7
6
5
4
3
2
1
0
RESERVED
ANA_GAIN
R/W
R/W
Table 8-34. AGAIN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
This bit is reserved
4-0
ANA_GAIN
R/W
00000
Analog Gain Control
This bit controls the analog gain.
00000: 0 dB (29.5V peak voltage)
00001:-0.5db 11111: -15.5 dB
8.6.1.26 PVDD_ADC Register (Offset = 5Eh) [reset = 0h]
PVDD_ADC is shown in Figure 8-39 and described in Table 8-35.
Return to Table 8-8.
Figure 8-39. PVDD_ADC Register
7
6
5
4
3
2
1
0
ADC_DATA_OUT
R
www.ti.com
TAS5828M
SLASEX7A – JUNE 2021 – REVISED DECEMBER 2021
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: TAS5828M



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com