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TAS5828M Datasheet(PDF) 64 Page - Texas Instruments |
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TAS5828M Datasheet(HTML) 64 Page - Texas Instruments |
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64 / 97 page  Table 8-35. PVDD_ADC Register Field Descriptions Bit Field Type Reset Description 7-0 PVDD_ADC[7:0] R 00000000 PVDD Voltage = PVDD_ADC[7:0] / 8.428 (V) 223: 26.45V 222: 26.34V 221:26.22V ... 39: 4.63V 38: 4.51V 37: 4.39V 8.6.1.27 GPIO_CTRL Register (Offset = 60h) [reset = 0x00] GPIO_CTRL is shown in Figure 8-40 and described in Table 8-36. Return to Table 8-8. Figure 8-40. GPIO_CTRL Register 7 6 5 4 3 2 1 0 RESERVED GPIO0_OE GPIO2_OE GPIO1_OE R/W R/W R/W R/W Table 8-36. GPIO_CTRL Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0000 This bit is reserved 2 GPIO0_OE R/W 0 GPIO2 Output Enable. This bit sets the direction of the GPIO0 pin 0: GPIO0 is input 1: GPIO0 is output 1 GPIO2_OE R/W 0 GPIO2 Output Enable This bit sets the direction of the GPIO2 pin 0: GPIO2 is input 1: GPIO2 is output 0 GPIO1_OE R/W 0 GPIO1 Output Enable This bit sets the direction of the GPIO1 pin 0: GPIO1 is input 1: GPIO1 is output 8.6.1.28 GPIO1_SEL Register (Offset = 61h) [reset = 0x00] GPIO1_SEL is shown in Figure 8-41 and described in Table 8-37. Return to Table 8-8. Figure 8-41. GPIO1_SEL Register 7 6 5 4 3 2 1 0 RESERVED GPIO1_SEL R/W R/W Table 8-37. GPIO1_SEL Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0000 This bit is reserved TAS5828M SLASEX7A – JUNE 2021 – REVISED DECEMBER 2021 www.ti.com 64 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TAS5828M |
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