ADAQ23876BBCZ datasheet(32/37 Pages) AD

32 / 37 page

Data Sheet

ADAQ23876

DIGITAL INTERFACE

analog.com

Rev. 0 | 32 of 37

The ADAQ23876 conversion is controlled by the CNV+ and CNV–

inputs, which can be driven directly with an LVDS signal. Alterna-

tively, the CNV+ pin can be driven with a 0 V to 2.5 V CMOS signal

when CNV– is connected to GND. A rising edge on CNV+ samples

the analog inputs and initiates a conversion. The pulse width of

CNV+ must meet the tCNVH and tCNVL specifications in the timing

table (see Table 2).

After the ADAQ23876 is powered on or exits power-down mode,

conversion data is invalid for the first two conversion cycles. The

subsequent conversion results are accurate as long as the time

between conversions meets the tCYC specification. If the analog

input signal has not completely settled when it is sampled, the

ADAQ23876 noise performance is affected by jitter on the rising

edge of CNV+. In this case, drive the rising edge of CNV+ with a

clean, low jitter signal. Note that the ADAQ23876 is less sensitive to

jitter on the falling edge of CNV+. In applications that are insensitive

to jitter, CNV can be driven directly from a field programmable gate

array (FPGA).

The ADAQ23876 has an internal clock that is trimmed to achieve a

maximum conversion time of 63 ns. With a typical acquisition time

of 27.7 ns, throughput performance of 15 MSPS is achieved.

The ADAQ23876 has a serial LVDS digital interface that is easy to

connect to an FPGA. Three LVDS pairs are required: CLK±, DCO±,

and DA±. A fourth LVDS pair, DB±, is optional (see Figure 83).

Route the LVDS signals on the PCB as 100 Ω differential transmis-

sion lines and terminated at the receiver with 100 Ω resistors. The

optional LVDS output, DB±, is enabled, and data is output two bits

at a time on DA± and DB±. Enabling the DB± output increases the

supply current from VIO by about 3.6 mA. In two-lane mode, four

clock pulses are required for CLK± (see Figure 87).

Figure 83. Digital Output Interface to an FPGA

ONE-LANE OUTPUT MODE

A conversion is started by the rising edge of CNV+. When the

conversion is complete, the most significant data bit is output on

DA±. Data is then ready to be shifted out by applying a burst of

eight clock pulses to the CLK± input. The data on DA± is updated

by every edge of CLK±. An echoed version of CLK± is output on

DCO±. The edges of DA± and DCO± are aligned. Therefore, DCO±

can be used to latch DA± in the FPGA. The timing of a single

conversion is shown in Figure 84 and Figure 85. Data must be

clocked out after the current conversion is complete, and before

the next conversion finishes. The valid time window for clocking out

data is shown in Figure 86. Note that it is allowed to be still clocking

out data when the next conversion begins.

TWO-LANE OUTPUT MODE

At high sample rates, the required LVDS interface data rate can

reach >400 Mbps. Most FPGAs can support this rate, but if a lower

data rate is desired, the two-lane output mode can be used. When

the TWOLANES input pin is connected high (VIO), the ADAQ23876

outputs two bits at a time on DA−/DA+ and DB−/DB+, as shown in

Figure 87.

ADAQ23876BBCZ Datasheet(PDF) 32 Page - Analog Devices

ADAQ23876BBCZ Datasheet(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Datasheet Download

Link URL