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ADAQ23876BBCZ Datasheet(PDF) 7 Page - Analog Devices |
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ADAQ23876BBCZ Datasheet(HTML) 7 Page - Analog Devices |
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7 / 37 page ![]() Data Sheet ADAQ23876 SPECIFICATIONS analog.com Rev. 0 | 7 of 37 TIMING SPECIFICATIONS VDD = 5 V ± 5%, VS+ = 5 V ± 5%, VS− = −1 V ± 5%, VS− = 0 V (95% of VIN), VIO = 2.375 V to 2.625 V, REFBUF = 4.096 V, sampling frequency (fS) = 15 MSPS, gain = 0.37, 0.73, 0.87, 1.38, and 2.25, and all specifications TMIN to TMAX, unless otherwise noted. Table 2. Digital Interface Timing Parameter Symbol Min Typ Max Unit Sampling Frequency fSMPL 0.02 15 MSPS Conversion Time—CNV± Rising Edge to Data Available tCONV 54 58 63 ns Acquisition Phase tACQ tCYC − 39 ns Time Between Conversions tCYC 66.6 50,000 ns CNV± High Time tCNVH 5 ns CNV± Low Time tCNVL 8 ns CNV± Rising Edge to First CLK± Rising Edge from the Same Conversion tFIRSTCLK 65 ns CNV± Rising Edge to Last CLK± Falling Edge from the Previous Conversion tLASTCLK 49 ns CLK± to DCO± Delay tCLKDCO 0.7 1.3 2.3 ns CLK± Low Time tCLKL 1.25 ns CLK± High Time tCLKH 1.25 ns CLK± to DA±/DB± Delay tCLKD 0.7 1.3 2.3 ns DCO± to DA±/DB± Skew tSKEW −200 0 +200 ps Sampling Delay Time tAP 0 ns Sampling Delay Jitter tJITTER 0.25 psRMS Timing Diagrams Figure 2. One-Lane Output Mode Timing Diagram |
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