SPC582BX datasheet(10/115 Pages) STMICROELECTRONICS

10 / 115 page

Description

SPC582Bx

10/115

DS11597 Rev 4

2.3

Feature overview

On-chip modules within SPC582Bx include the following features:

•

One main CPU, single issue, 32-bit CPU core complexes (e200z2).

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Power Architecture embedded specification compliance

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Instruction set enhancement allowing variable length encoding (VLE), encoding a

mix of 16-bit and 32-bit instructions, for code size footprint reduction

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Single-precision floating point operations

•

1088 KB (1024 KB code flash + 64 KB data flash) on-chip Flash memory

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Supports read during program and erase operations, and multiple blocks allowing

EEPROM emulation

•

96 KB on-chip general-purpose SRAM

•

Multi channel direct memory access controllers

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16 eDMA channels

•

One interrupt controller (INTC)

•

Dual phase-locked loops with stable clock domain for peripherals and FM modulation

domain for computational shell

•

Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from

multiple bus masters with end-to-end ECC

•

System integration unit lite (SIUL)

•

Boot assist Flash (BAF) supports factory programming using a serial bootload through

the asynchronous CAN or LIN/UART.

•

Hardware support for safety ASIL-B level related applications

•

Enhanced modular IO subsystem (eMIOS): up to 32 timed I/O channels with 16-bit

counter resolution

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Buffered updates

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Support for shifted PWM outputs to minimize occurrence of concurrent edges

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Supports configurable trigger outputs for ADC conversion for synchronization to

channel output waveforms

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Shared or independent time bases

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DMA transfer support available

•

Body cross triggering unit (BCTU)

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Triggers ADC conversions from any eMIOS channel

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Triggers ADC conversions from up to 2 dedicated PIT_RTIs

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One event configuration register dedicated to each timer event allows to define the

corresponding ADC channel

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Synchronization with ADC to avoid collision

•

One 12-bit SAR analog-to-digital converter

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up to 27 channels

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enhanced diagnosis features

•

Four deserial serial peripheral interface (DSPI) modules

•

Six LIN and UART communication interface (LINFlexD) modules

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LINFlexD_0 is a Master/Slave

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All others are Masters

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