AD3552R datasheet(63/68 Pages) AD

63 / 68 page

Data Sheet

AD3552R

REGISTERS

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Rev. A | 63 of 68

Channel Select for Page Registers, Precision Mode

Address: 0x41, Reset: 0x00, Name: CH_SELECT_24B

This register selects which channel registers are updated following a write to the DAC_PAGE_24B or INPUT_PAGE_24B registers.

Table 56. Bit Descriptions for CH_SELECT_24B

Bits

Bit Name

Settings

Description

Reset

Access

[7:2]

RESERVED

Reserved.

0x0

SEL_CH1

Select Channel 1. When this bit is set, data written to the INPUT_PAGE_24B register is

copied to the CH1_INPUT_24B register and data written to the DAC_PAGE_24B register is

copied to the CH1_DAC_24B register.

0x0

R/W

0 No operation.

1 Copy to corresponding register in Channel 1.

SEL_CH0

Select Channel 0. When this bit is set, data written to the INPUT_PAGE_24B register is

copied to the CH0_INPUT_24B register and data written to the DAC_PAGE_24B register is

copied to the CH0_DAC_24B register.

0x0

R/W

0 No operation.

1 Copy to corresponding register in Channel 0.

Input Page Register, Precision Mode

Address: 0x42, Reset: 0x000000, Name: INPUT_PAGE_24B

This register is used to write data to one or both DAC input registers according to the configuration of the SEL_CHx bits in the CH_SE-

LECT_24B register.

Table 57. Bit Descriptions for INPUT_PAGE_24B

Bits

Bit Name

Settings

Description

Reset

Access

[23:8]

INPUT_PAGE

Input Page Data. Following a write to this register, the DAC code loaded into this register

is copied into the input register of any channels selected in the CH_SELECT_24B

0x0

R/W

[7:0]

RESERVED

Reserved.

0x0

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