AD3552R datasheet(26/68 Pages) AD

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Data Sheet

AD3552R

THEORY OF OPERATION

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The AD3552R SPI protocol is flexible and can be configured to suit

the needs of a variety of digital hosts. Data from multiple registers

can be accessed in a single SPI frame, enabling efficient device

configuration. All the different access modes are described in the

Single Instruction Mode section and the Streaming Mode section.

Instruction Phase

Every SPI frame starts with an instruction phase. The instruction

phase immediately follows the falling edge of CS that initiates the

SPI transaction.

The instruction phase consists of a read/write bit (R/W) followed

by a register address word. Setting R/W low initiates a write

instruction, whereas setting R/W high initiates a read instruction.

The register address word specifies the address of the register to

be accessed. The register address word is 7 bits in length (7‑bit

addressing) by default. If required, 15‑bit addressing can be ena-

bled by setting the SHORT_INSTRUCTION bit to 0 in the INTER-

FACE_CONFIG_B register. If the user is using single instruction

mode, each register read or write transaction in a single SPI frame

also begins with an instruction phase. If the user is using streaming

mode, only one instruction phase is required per SPI frame to

access a set of consecutive registers. See the Single Instruction

Mode section and the Streaming Mode section for instructions on

selecting and using these modes.

Data Phase

The data phase immediately follows the instruction phase, as

shown in Figure 68 and Figure 69. The data phase can include

the data for a single-byte register, a multibyte register, or multiple

registers depending on the selected registers and access modes.

See the Single Instruction Mode section, Streaming Mode section,

and Address Direction section for descriptions of how these modes

affect the read and write data in the data phase.

In a write operation, the content of the addressed register is updat-

ed immediately after the SCLK edge, which shifts in the last bit

of the register data, regardless if it is a one-byte, two-byte, or

three-byte register. Multibyte registers cannot be written partially, as

explained in the Multibyte Registers section.

In a read operation, the content of the addressed register starts

shifting out on the first SCLK edge of the data phase.

Data must be written to the AD3552R configuration registers in full

bytes to ensure they are updated. If the data phase of an SPI write

transaction does not include the entire byte of data for the register

being updated, the contents of the register are not updated, and the

CLOCK_COUNTING_ERROR bit in the INTERFACE_STATUS_A

Figure 68. Basic SPI Write Frame

Figure 69. Basic SPI Read Frame

Multibyte Registers

Some AD3552R registers consist of 2 or 3 bytes of data stored

in adjacent addresses and are referred to as multibyte registers.

Multibyte registers end with a 16B or 24B suffix when they are 2

bytes or 3 bytes, respectively.

When writing to a multibyte register of the AD3552R, all bytes must

be transferred in a single SPI transaction. For this reason, the

STRICT_REGISTER_ACCESS bit in the INTERFACE_ CONFIG_C

multibyte register is attempted on a per byte basis, the register con-

tents are not updated and the PARTIAL_REGISTER_ACCESS bit

in the INTERFACE_ STATUS_A register is set. A write transaction

to a multibyte register of the AD3552R takes effect after the 24th or

16th SCLK edge of the data phase, which shifts in the last bit of the

Figure 70. Multibyte Register Write with Ascending Addressing

Figure 71. Multibyte Register Read with Descending Addressing

The address of a multibyte register always depends on the

ADDR_ASCENSION bit in the INTERFACE_CONFIG_A register

(see the Address Direction section for more details). With descend-

ing addressing, the first byte accessed in the data phase must

be the most significant byte of the multibyte register, and each

subsequent byte corresponds to the data in the next lower address.

With ascending addressing, the first byte accessed in the data

phase must be the least significant byte of the multibyte register,

and each subsequent byte corresponds to the data in the next

higher address.

Multibyte registers can be read in a single SPI transaction or each

byte can be addressed separately. If an SPI read transaction to

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