AD3552R datasheet(67/68 Pages) AD

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Data Sheet

AD3552R

APPLICATIONS INFORMATION

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Rev. A | 67 of 68

Figure 94. EVAL-AD3552R Component Arrangement and Layout

The following list is a few recommendations to observe to obtain the

best performance:

►

Keep IOUT lines as short and thin as possible. This signal is

responsible for the slewing of the amplifier to the final value.

Therefore, the parasitic capacitance on this line increases the

settling time. Use a feedback capacitor with a small footprint to

minimize parasitic capacitance to the ground plane.

►

Keep the IOUT line away from repetitive signals, such as clocks

and analog signals with high voltage excursion, because this is

a high impedance line that can easily pick up electromagnetic

interference.

►

Connect the exposed pad of the AD3552R to the ground plane

with several vias to minimize thermal drift. Note that the chip can

dissipate up to 250 mW.

►

Do not overlap analog and digital signals. If a crossing cannot be

avoided, it must be done at 45° or 90°.

►

Route digital lines using traces with a constant characteristic

impedance to avoid signal integrity problems that result in timing

violations in DDR mode and crosstalk between signals. The

traces must have a continuous ground plane underneath. When

changing layers, ensure that the destination layer is referred to

another ground plane and the traces have the same characteris-

tic impedance. Place a via connecting both ground planes near

the via of the digital line. If the destination layer is referred to

a power plane, it must be continuous along the path of the line

and a decoupling capacitor between power and ground must be

placed close to the via of the digital line.

AD3552R Datasheet(PDF) 67 Page - Analog Devices