AD3552R datasheet(28/68 Pages) AD

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Data Sheet

AD3552R

THEORY OF OPERATION

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Rev. A | 28 of 68

Streaming Mode

When the SINGLE_INSTRUCTION bit in the INTERFACE_CON-

FIG_B register is set to 0, single instruction mode is disabled and

streaming mode is enabled. In streaming mode, multiple registers

with adjacent addresses can be accessed with a single instruction

phase and data phase, allowing efficient access of contiguous

regions of memory (for example, during initial device configuration).

The AD3552R is configured in streaming mode by default.

When in streaming mode, each SPI frame consists of a single in-

struction phase and the following data phase contains data for mul-

tiple registers with adjacent addresses. A starting register address

is specified by the digital host in the instruction phase, and this

address is automatically incremented or decremented (based on

the address direction setting) after each byte of data is accessed.

The data phase can, therefore, be multiple bytes long, and each

consecutive byte of read or write data corresponds to the next

higher or lower register address (for ascending and descending

address direction, respectively).

When writing or reading from a multibyte register in streaming

mode with address ascending, the user must address the least

significant byte of the register in the instruction phase. The data

phase starts transferring data from the least significant byte in first

place.

When writing or reading from a multibyte register in streaming

mode with the address descending, the user must start addressing

the most significant byte of the register in the instruction phase. The

data phase starts transferring the most significant byte in first place.

Figure 73 shows the instruction and data phase when using stream-

ing mode with address descending to write some registers of the

AD3552R starting from Address 0x16. The length of the data

phase determines the number of data bytes to be transferred to

consecutive addresses. CS is brought high at the end of the write

transaction (in Figure 73, the end of the write transaction occurs

after Address 0x02).

Figure 74 shows the instruction and data phase when using stream-

ing mode with address ascending to read some registers of the

AD3552R starting from Address 0x16. The length of the data

phase determines the number of data bytes to be transferred to

consecutive addresses. CS is brought high at the end of the read

transaction (in Figure 74, the end of the read transaction occurs

after Address 0x02).

The STREAM_MODE register can be used to specify a range of

consecutive registers to loop through in the data phase. Looping

allows the digital host to repeatedly read from or write to a set of

registers (for example, CHx_DAC_16B register at Address 0x29 to

Address 0x2C) as efficiently as possible. When accessing register

addresses after and including Address 0x29, the address direction

must always be set as descending.

If STREAM_MODE is set to 0, looping is disabled and the following

occurs:

►

If address direction is set to descending, the address decre-

ments until it reaches 0x00. On the subsequent byte accesses,

the address is set to the top of the addressable space (Address

0x4B). Note that restrictions may apply in terms of SPI mode

access depending on the register address.

►

If address direction is set to ascending, the address increments

until it reaches the top of the addressable space (Address 0x4B).

On the subsequent byte access, the address is reset to 0x00.

Note that restrictions may apply in terms of SPI mode access

depending on the register address. Multibyte registers greater

than 0x28 do not update in ascending mode.

If STREAM_MODE is set to a value other than 0, looping is enabled

and the value corresponds to the number of bytes to be accessed

in the data phase before the address loops back to the value

specified in the address phase. An example is shown in Figure 75.

The value of the STREAM_MODE register can be preserved or

reset to 0 at the end of the transaction (when CS returns high)

depending on the value of the STREAM_LENGTH_KEEP_VALUE

bit in the TRANSFER_REGISTER, as shown in Table 10.

Table 10. Stream Mode Autoreset

STREAM_LENGTH_KEEP_VALUE

STREAM_MODE Register

Autoreset

Keeps previous value

Figure 73. Streaming Mode Register Write with Address Descending

Figure 74. Streaming Mode Register Read with Looping Disabled

AD3552R Datasheet(PDF) 28 Page - Analog Devices

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