RT600 datasheet(126/167 Pages) NXP

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RT600

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Product data sheet

Rev. 2.0 — 1 April 2022

126 of 165

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

14.14 SD/MMC and SDIO

Table 46.

Dynamic characteristics for following modes (SDR-12, SDR-25)

Tamb =0 °C to +85 °C, VDDIO_x = 1.71 V to 1.89 V; VDDCORE = 1.13 V; CL = 10 pF. DLL_CTRL = 0x200, Full Drive Mode

on all pins, Input slew = 1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the rising

or falling edge. Based on simulation, not tested in production.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fclk

clock frequency

on pin SD_CLK; data transfer mode,

SDR-12 (12.5 MB/s)

MHz

fclk

clock frequency

on pin SD_CLK; data transfer mode,

SDR-25 (25 MB/s)

MHz

tsu(D)

data input set-up time

on pins SD_DATn as inputs

7.5

on pins SD_CMD as inputs

7.5

th(D)

data input hold time

on pins SD_DATn as inputs

on pins SD_CMD as inputs

tv(Q)

data output valid time

on pins SD_DATn as outputs

7.5

on pins SD_CMD as outputs

7.5

Table 47.

Dynamic characteristics for following modes (SDR-50, SDR-104, SDR-200(HS-200))

Tamb =-0 °C to +85 °C, VDDIO_x = 1.71 V to 1.89 V; VDDCORE = 1.13 V; CL = 10 pF. DLL_CTRL = 0x200, Full Drive Mode

on all pins, Input slew = 1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the rising

or falling edge. Based on simulation, not tested in production.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fclk

clock frequency

on pin SD_CLK; data transfer mode,

SDR-50 (50 MB/s)

100

MHz

fclk

clock frequency

on pin SD_CLK; data transfer mode,

SDR-104 (104 MB/s)

208

MHz

fclk

clock frequency

on pin SD_CLK; data transfer mode,

SDR-200 (HS-200) (200 MB/s)

200

MHz

tsu(D)

data input set-up time

on pins SD_DATn as inputs

7.5

on pins SD_CMD as inputs

7.5

th(D)

data input hold time

on pins SD_DATn as inputs

on pins SD_CMD as inputs

tv(Q)

data output valid time

on pins SD_DATn as outputs

7.5

on pins SD_CMD as outputs

7.5

Table 48.

Dynamic characteristics for following modes (DDR-50, DDR-100, HS DDR)

Tamb =-0 °C to +85 °C, VDDIO_x = 1.71 V to 1.89 V; VDDCORE = 1.13 V; CL = 10 pF. DLL_CTRL = 0x200, Full Drive Mode

on all pins, Input slew = 1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the rising

or falling edge. Based on simulation, not tested in production. HS-400 supported on SD port 0 only.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fclk

clock frequency

on pin SD_CLK; data transfer mode,

DDR-50 (50 MB/s)

MHz

fclk

clock frequency

on pin SD_CLK; data transfer mode,

DDR-100 (100 MB/s)

MHz

fclk

clock frequency

on pin SD_CLK; data transfer mode, HS

DDR (104 MB/s)

MHz

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