LM5072 datasheet(18/24 Pages) NSC

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RAUX Option (Continued)

actually be removed by the PSE, although the DC current

from the network cable is effectively reduced to zero (< 150

µA). IEEE 802.3af requires the AC input impedance to be

greater than 2 M

Ω to ensure PoE power removal. This

condition is not satisfied when the auxiliary power source is

applied. The PSE may remove power from a port based on

the reduction in DC current. This is commonly known as DC

Maintain Power Signature (DC MPS), a common feature in

many PSE systems.

The high voltage startup regulator of the PWM controller

does not have low dropout capability and will not be able to

provide V

CC when the potential from VIN to RTN is less than

14.5V (no external V

CC load). In this case, the auxiliary

voltage should supply V

CC directly via diode OR-ing to en-

sure successful startup.

When using the RAUX configuration, the positive potential

connection of the 0.1 µF signature capacitor should be

moved from VIN to RTN/ARTN as shown in Figure 11. This

provides a high frequency, low impedance path for the IC’s

substrate during rear auxiliary opration. Placing the capacitor

here will not affect signature mode.

It should be noted that rear auxiliary non-dominance does

not imply PoE dominance. PoE dominance is difficult to

achieve in any PoE system if continuity of power is desired.

When the PoE voltage appears, the PSE and PD interface

must continue delivering load current in addition to charging

the input capacitor bank from the auxiliary voltage to the PoE

voltage. The situation is further complicated by the fact that

for a given delivered power level, the load current is much

higher at the lower input voltages typically used in auxiliary

supplies. As is the case during any inrush sequence, very

high power is dissipated in the hot swap MOSFET. Conse-

quently, attempting to achieve inrush completion while deliv-

ering load current is highly ill advised. Lastly, current deliv-

ered to the system may be limited by the PSE, the PD, or

both.

A Note About FAUX and RAUX Pin

False Input State Detection

The ICL_FAUX and RAUX pins are used to sense the pres-

ence of auxiliary power sources. The input voltage of each

pin must remain low when the auxiliary power sources are

absent. However, the Or-ing diodes feeding the auxiliary

power are not ideal and leak reverse current that can flow

from the PoE input to both the ICL_FAUX and RAUX pins.

When PoE power is applied, these leakage currents may

elevate the potentials of the ICL_FAUX and RAUX pins to

false logic states.

One of two failure modes may be observed when the power

diode feeding the front auxiliary input leaks excessively.

First, the current may corrupt the inrush current limit pro-

gramming, if that feature has been implemented. Second,

the leakage current may elevate the voltage on the pin to the

ICL_FAUX input threshold, which will force UVLO release.

This would certainly interrupt any attempt by the LM5072 PD

interface to perform the signature or classification functions.

When the power diode that feeds the rear auxiliary input

leaks, the false signal could imply a rear auxiliary supply is

present. In this case, the internal hot swap MOSFET will be

turned off. This would of course block PoE power flow and

cause the circuit to prevent startup.

This leakage problem at the control input pins can be easily

solved. As shown in Figure 12, an additional pull-down re-

sistor (Rpd) across each auxiliary power control input pro-

vides a path for the diode leakage current so that it will not

create false states on the ICL_FAUX or RAUX pins.

High Voltage Startup Regulator

The LM5072 contains a startup bias regulator that allows the

VIN pin to be connected directly to PoE network voltages as

high as 100V. The regulator output is connected to the VCC

pin, providing an initial DC bias voltage of 7.7V nominal to

start the PWM controller. The regulator is internally current

limited to no less than 15 mA to prevent excessive power

dissipation. For V

CC voltage stability and noise immunity, a

capacitor ranging between 0.1 µF to 10 µF is required be-

tween the VCC and ARTN pins. Though the current capabil-

ity of the regulator exceeds the requirements of the IC, no

external DC load drawing more than 3 mA should be applied

to the output. A small amount of current for a “Powered from

PoE” indicator LED (see Power Good section) is acceptable.

After the DC-DC converter reaches steady state operation,

the V

CC voltage is typically elevated by an auxiliary winding

of the power transformer. The sustained V

CC voltage should

be greater than 8.1V to guarantee the current supplied by

the startup regulator is reduced to zero. Increasing the VCC

pin voltage above the regulation level of the startup regulator

automatically disables the regulator, thus reducing the power

dissipation inside the LM5072. The power savings can be

significant as many high voltage MOSFETs require a rela-

tively large amount of gate charge and the gate drive current

adds directly to the V

CC current draw.

CC under-voltage lock-out circuit monitors the VCC volt-

age to prevent the PWM controller from operating as the V

voltage rises during startup or falls during shutdown. The

PWM controller is enabled when the V

CC voltage rising edge

exceeds 7.6V and disabled when the V

CC voltage falling

edge drops below 6.25V.

Error Amplifier

The LM5072 contains a wide-bandwidth, high-gain error am-

plifier to regulate the output voltage in non-isolated applica-

tions. The amplifier’s non-inverting input is set to a fixed

reference voltage of 1.25V, while the inverting input is con-

nected to the FB pin. The open-drain output of the amplifier

is connected to the COMP pin, which is pulled up internally

througha5k

Ω resistor to an internal 5V bias voltage.

Feedback loop compensation can be easily implemented by

placing the compensation network, represented by “Zcomp”,

between the FB and COMP pins as shown in Figure 13.

20184629

FIGURE 12. Bypassing Resistor – Prevents False

ICL_FAUX and RAUX Pin Signaling

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