LM5072 datasheet(15/24 Pages) NSC

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Power Good and Regulator Startup (Continued)

The nPGOOD pin can be configured to perform multiple

functions. As shown in Figure 9, it can be used to implement

a “Powered from PoE” indicator using an LED with a series

current limiting resistor connected to the VCC pin. This may

be useful when the auxiliary power source is directly con-

nected to the DC-DC converter stage, a situation known as

“RAUX” (see Auxiliary Power Options below). In such a

configuration, the nPGOOD pin will be active when the PD is

operating from PoE power but not when it is powered from

the auxiliary source. However, the “Powered from PoE” indi-

cator is not applicable in systems implementing the front

auxiliary power configuration “FAUX” (see Auxiliary Power

Options below) because both PoE and auxiliary supply cur-

rent pass through the hot swap MOSFET. In this configura-

tion, the nPGOOD pin is active when either PoE power or

auxiliary power is applied. The designer should ensure that

the current drawn by the LED is not more than a few milli-

amps, as the V

CC regulator’s output current is limited to 15

mA and must also supply the LM5072’s bias current and

external MOSFET’s gate charging current. Supplying an

external V

CC that is higher than the regulated level with a

bench supply is an easy way to measure VCC load during

normal operation. It should also be noted that an external

load on the V

CC line will increase the dropout voltage of the

CC regulator. This may be a concern when operating from a

low voltage rear auxiliary supply.

The nPGOOD pin can also be used to implement a delay

timer by adding a capacitor from the nPGOOD pin to the

ARTN pin. This delay timer will prevent the interruption of the

PWM controller’s operation in the event of an intermittent

loss of Power Good status. This can be caused by PoE line

voltage transients that may occur when switching between

normal PoE power and a backup supply system (e.g. a

battery or UPS). This condition will create a new “hot swap”

event if there is a voltage difference between the backup

supply and PoE supply. Since the hot swap MOSFET will

likely limit current during such a sudden input voltage

change, the nPGOOD pin will momentarily switch to the ”pull

up” state. A capacitor on this pin will delay the transition of

the nPGOOD pin state in order to provide continuous opera-

tion of the PWM controller during such transients. The Power

Good filter delay time and capacitor value can be selected

with the following equation:

For example, selecting 1000 nF for C

PGOOD, the delay time

will be 50 ms if no LED is used and about 0.83 ms when an

LED, drawing 3 mA, is used. The delay required for contin-

ued operation will depend on the amplitude of the transient,

the DC current limit, the load, and the total amount of input

capacitance. Note that this delay does not guarantee contin-

ued operation. If the hot swap MOSFET is in current limit for

an extended period, it may cause a thermal limit condition.

This will result in a complete shutdown of the switching

regulator, though no elements in the system will be perma-

nently damaged and normal operation will resume momen-

tarily.

The Power Good status will also affect the default DC cur-

rent limit. Should the sensed drain to source voltage of the

hot swap MOSFET (from ARTN to V

EE) exceed 2.5V, the

LM5072 will increase the DC current limit from the default

440 mA to 540 mA, thus allowing the PD to continue opera-

tion through the transient event. This higher current limit will

remain in effect until one of the following events occur: (i) the

duration of loss of Power Good status exceeds t

PG_Delay,at

which time the PWM controller will be disabled, (ii) the

increased power dissipation in the hot swap MOSFET

causes a thermal limit condition as previously discussed, or

(iii) the MOSFET drain to source voltage falls below 1.5V to

re-establish Power Good status. Under this condition, the

LM5072 will revert back to the default 440 mA DC current

limit once Power Good status is restored. Note that if the DC

current limit has been programmed externally with R

DCCL

(see the DC current limit section), the DC current limit will

remain at the programmed level even when the Power Good

status is lost.

20184625

FIGURE 9. "Powered-from-PoE" Indictor and Power Good Delay Timer

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