LM5072 datasheet(13/24 Pages) NSC

13 / 24 page

Classification (Continued)

LM5072 is operated at elevated ambient temperatures and

the classification time exceeds the IEEE802.3af limit of 75

ms.

When the classification option is not required, simply leave

the RCLASS pin open to set the PD to the default Class 0

state. Class 0 requires that the PSE allocate the maximum

IEEE802.3af specified power of 15.4 W (12.95 W at the PD

input terminals) to the PD.

Undervoltage Lockout (UVLO)

The LM5072’s internal preset UVLO circuit continuously

monitors the PoE input voltage between the VIN and VEE

pins. When the V

IN voltage rises above 38V nominal, the

UVLO circuit will release the hot swap MOSFET and initiate

the startup inrush sequence. When the V

IN voltage falls

below 31V nominal during normal operating mode, the

LM5072 disables the PD by shutting off the hot swap

MOSFET.

Figure 6 illustrates the block diagram of the LM5072 UVLO

circuit. This function requires no external components. The

UVLO signal can be over-ridden by the front auxiliary power

option (see details in the FAUX section) to allow the hot

swap MOSFET of the LM5072 to pass power from front

auxiliary power sources at voltage levels below the PoE

operating voltage. In the rear auxiliary power application

(see RAUX section), the auxiliary power source bypasses

the hot swap MOSFET and is applied directly to the input of

the DC-DC converter. The UVLO function does not need to

be over-ridden in this configuration.

The PD can draw a maximum current of 400 mA during

standard 802.3af PoE operation. This current will cause a

voltage drop of up to 8V over a 100m long Ethernet cable.

The PD front-end current steering diode bridges may intro-

duce an additional 2V drop. In order to guarantee successful

startup at the minimum PoE voltage of 42V, and to continue

operation at the minimum requirement of 36V as specified by

IEEE 802.3af, these voltage drops must be taken into ac-

count. Therefore, the LM5072 UVLO thresholds have been

set to 38V on the rising edge of VIN, and 31V on the falling

edge of VIN. The 7V nominal hysteresis of the UVLO func-

tion, in addition to the inrush current limit (discussed in the

next section), prevents false starts and chattering during

startup.

Inrush Current Limit Programming

According to IEEE 802.3af, the input capacitance of the PD

power supply must be at least 5 µF (between the VIN and

RTN pins). Considering the capacitor tolerance and the ef-

fects of voltage and temperature, a nominal capacitor value

of at least 10 µF is recommended to ensure 5 µF minimum

under all conditions. A greater amount of capacitance may

be needed to filter the input ripple of the DC-DC converter.

The input capacitors remain discharged during detection and

classification modes of the PD interface. The hot swap MOS-

FET is turned on after the VIN minus VEE voltage difference

rises above the UVLO release threshold of 38V nominal.

When enabled, the hot swap MOSFET delivers a regulated

inrush current to charge the input capacitors of the DC-DC

converter. To prevent excessive inrush current, the LM5072

20184620

FIGURE 6. Preset Input UVLO Function

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