LM5072 datasheet(20/24 Pages) NSC

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Soft-Start (Continued)

external capacitor. Note that the slope of the supply’s output

voltage is influenced by the load condition and the total

output capacitance of the supply, as well as the soft-start

programming. The supply should be started slowly enough

such that the input current is limited below the hot swap

MOSFET DC current limit.

Gate Driver and Maximum Duty

Cycle Limit

The LM5072’s gate drive (OUT) pin can source and sink a

peak current of 800 mA directly to the gate of the DC-DC

converter’s power MOSFET switch. To serve a variety of

applications, the LM5072 is available with two options for

maximum PWM duty cycle. The LM5072-80 operates at duty

cycles up to 80% while the LM5072-50 limits the PWM duty

cycle to 50%.

Oscillator, Shutdown and Sync

Capability

The LM5072 requires a single external resistor connected

between the RT and ARTN pins to set the oscillator fre-

quency (F

OSC). The RT timing resistor should be located

very close to the IC and connected directly to the RT and

ARTN pins. The following equation describes the relation-

ship between F

OSC and the RT resistor value:

The LM5072 can also be synchronized to an external clock

signal with a frequency higher than the programmed oscilla-

tor frequency determined by the R

T resistor. The clock signal

should be coupled into the RT pin through a 100 pF capaci-

tor, as shown in Figure 17. Successful synchronization re-

quires the peak voltage of the sync pulse signal to be greater

than 3.7V at the RT pin, and pulse width between 15 and 150

ns (set by external components). The R

T resistor is always

required, whether the oscillator is operated in “free-running”

mode or with external synchronization.

Special attention should be paid to the relationship between

the oscillator frequency and the PWM switching frequency.

For the LM5072-50 version, the programmed oscillator fre-

quency is internally divided by two in order to facilitate the

50% duty cycle limit. The PWM output switching frequency is

therefore one half of the programmed oscillator frequency.

The frequency divider is not used in the LM5072-80 and

therefore the PWM output frequency is the same as the

oscillator frequency. These relationships also apply to exter-

nal synchronization frequency versus PWM output fre-

quency.

PWM Comparator / Slope

Compensation

The PWM comparator produces the PWM duty cycle by

comparing the current sense ramp signal with an error volt-

age derived from the error amplifier output. The error ampli-

fier output voltage at the COMP pin is offset by 1.4V and

then further attenuated by a 3:1 resistor divider before it is

presented to the PWM comparator input.

The PWM duty cycle increases with the voltage at the COMP

pin. The controller output duty cycle reduces to zero when

the COMP pin voltage drops below approximately 1.4V.

For duty cycles greater than 50%, current mode control

loops are subject to sub-harmonic oscillation. This instability

can be eliminated by adding an additional fixed slope voltage

ramp signal to the current sense signal. This technique is

commonly

known

“slope

compensation”.

For

the

LM5072-80 version with its maximum duty cycle of 80%,

slope compensation is integrated by injecting a 45 µA current

ramp from the oscillator into the current sense signal path

(see Figure 2). The 45 µA peak ramping current flows

through an internal 2 k

Ω resistor to produce a fixed voltage

ramp at the PWM comparator input. Additional slope com-

pensation may be added by increasing the source imped-

ance of the current sense signal with an external resistor

between the CS pin and the source of the current sense

signal. The feature is disabled for the LM5072-50 version

because the duty cycle is limited to 50% and slope compen-

sation is not required.

Thermal Protection

The LM5072 includes internal thermal shutdown circuitry to

protect the IC in the event the maximum junction tempera-

ture is exceeded. This circuit prevents catastrophic over-

heating due to accidental overload of the hot swap MOSFET

or other circuitry. Typically, thermal shutdown is activated at

165˚C, causing the hot swap MOSFET and classification

regulator to be disabled. The PWM controller is disabled

after the PGOOD timer has expired. Thermal limit is not

enabled unless the module is being powered through the

front end and the hot swap MOSFET is enhanced. V

current limit provides an adequate level of protection for this

15 mA regulator. The thermal protection is non-latching,

therefore after the temperature drops by the 25˚C nominal

hysteresis, the hot swap MOSFET is re-activated and a

soft-start is initiated to restore the LM5072 to normal opera-

tion. If the cause of overheating has not been eliminated, the

circuit will hiccup in and out of the thermal shutdown mode.

PCB Layout Guidelines

Before processing the Printed Circuit Board (PCB) layout,

the engineer should make all necessary adjustments to the

schematic to suite the application. The reader may notice

that the LM5072 evaluation board is designed with dual

outputs, both FAUX and RAUX power options, and some

re-configuration flexibility features (refer to Figure 19). How-

ever, many devices can be removed for a particular applica-

tion. Recommendations on simplifying Figure 19 to suit a

given application are as follows:

When selecting the FAUX power option only, delete C3,

D1, D2, J3, P3, P4, R1, R2, R13, and R29.

20184635

FIGURE 17. Oscillator Synchronization Implementation

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