Data Sheet

ADN4620/ADN4621

APPLICATIONS INFORMATION

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Rev. 0 | 20 of 24

PCB LAYOUT

The ADN4620/ADN4621 can operate with high speed LVDS signals

up to a 1.25 GHz clock, or a 2.5 Gbps nonreturn to zero (NRZ) da-

ta. When operating with such high frequencies, apply best practices

for the LVDS trace layout and termination. Place 100 Ω termination

Controlled impedance traces (100 Ω differential) are needed on

LVDS signal lines for full signal integrity, reduced system jitter,

and for minimizing electromagnetic interference (EMI) from the

PCB. Trace widths, lateral distance within each pair of traces, and

distance to the ground plane underneath all trace pairs must be

chosen appropriately. Via fencing to the PCB ground between pairs

is also a best practice to minimize crosstalk between adjacent pairs.

The ADN4620/ADN4621 have passed EN 55032 Class B emis-

sions limits when operating with up to 2.5 Gbps PRBS data, using a

high speed PCB design with an embedded PCB stitching capacitor

(constructed by overlapping internal PCB Layer 2 and Layer 3

under the area of the isolator). Depending on the system design,

or when isolating for high speed clocks, other EMC mitigation

measures may be required to provide a sufficient margin below

Class B emissions limits.

The best practice for high speed PCB design can minimize emis-

sions from traces with high speed LVDS signals. However, trace

lengths can be modified to avoid resonances at specific frequencies

when the traces act as an antenna for switching noise. Special

care is recommended for off-board connections, where switching

transients from high speed LVDS signals (and clocks in particular)

may conduct onto cabling, resulting in radiated emissions. Use

common-mode chokes, ferrites, or other filters as appropriate at

LVDS connectors and power supplies, as well as cable shield or

PCB ground connections to earth or chassis.

pins with 100 nF capacitors. Power supplies must also have appro-

priate filtering to avoid possible radiated emissions due to high

frequency switching noise.

APPLICATION EXAMPLES

High speed LVDS interfaces for the analog front-end (AFE), pro-

cessor to processor serial communication, or video and imaging

data can be isolated using the ADN4620/ADN4621 between com-

ponents, between PCBs, or at a cable interface.

The ADN4620/ADN4621 provide the galvanic isolation required for

robust external ports, and the low jitter and high drive strength

of the devices allow communication along short cable runs of a

few meters. High common-mode immunity ensures communication

integrity even in harsh, noisy environments, and isolation can pro-

tect against electromagnetic compatibility (EMC) transients up to

Standard LVDS inputs and outputs allow simple integration into

high speed signal chains using field-programmable gate arrays

(FPGAs) or application specific integrated circuits (ASICs), redriv-

ers, or coupling networks to interface to CML and other physical

layers.

Isolated AFE applications provide an example of the ADN4620/

ADN4621 isolating an LVDS interface between components. As

shown in Figure 35, two ADN4621 components isolate the LVDS

interface of the ADAQ23876 μmodule data acquisition solution,

including 800 Mbps data, 400 MHz echoed clock, and a 15 MHz

sample clock. The ADN4621 additive phase jitter is sufficiently

low that it does not affect the analog-to-digital converter (ADC)

performance even when isolating the sample clock. In addition,

implementing the galvanic isolation improves ADC performance

by removing digital and power supply noise from the FPGA/ASIC

circuit.

PCB to PCB connections and even cable interfaces can leverage

LVDS signaling for high bandwidth links with low latency synchro-

nous data transfer. Serialized gigabit Ethernet connections can be

isolated to robustly cascade Ethernet or multiprotocol switches for

industrial controller communication modules, as shown in Figure

36. The ADN4621 isolates the 1.25 Gbps transmit and receive

signal for two ports at each node to create a daisy chain topology.

The propagation delay of just over a couple of nanoseconds pro-

vides the low latency needed for industrial automation and process

control.

Figure 35. Isolated Analog Front-End Implementation Example (Isolated ADAQ23876 Using the ADN4621)