AFE7900IALK datasheet(87/157 Pages) TI

87 / 157 page

6.12.8 TX Typical Characteristics at 800MHz (continued)

Typical values at TA = +25°C with nominal supplies. Unless otherwise noted, TX input data rate = 491.52MSPS, fDAC =

11796.48MSPS, interleave mode, AOUT = –1 dBFS, 1st Nyquist zone output, Internal PLL, fREF = 491.52MSPS, 24x

Interpolation, DSA = 0 dB, Sin(x)/x enabled, Dither = 1, DSA calibrated, TX Clock Dither Enabled

DSA (dB)

0.05

0.1

0.15

0.2

1TX

2TX

3TX

4TX

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Integrated Phase Error = PhaseOUT(DSA Setting) –

PhaseOUT(DSA Setting = 0)

Figure 6-291. TX Uncalibrated Integrated Phase Error vs DSA

Setting and Channel at 0.85 GHz

DSA (dB)

-0.35

-0.3

-0.25

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

1TX

2TX

3TX

4TX

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Integrated Phase Error = PhaseOUT(DSA Setting) –

PhaseOUT(DSA Setting = 0)

Figure 6-292. TX Calibrated Integrated Phase Error vs DSA

Setting and Channel at 0.85 GHz

DSA (dB)

-0.02

-0.01

0.01

0.02

-40qC

25qC

105qC

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Differential Phase Error = PhaseOUT(DSA Setting – 1) –

PhaseOUT(DSA Setting) + 1

Figure 6-293. TX Uncalibrated Differential Phase Error vs DSA

Setting and Temperature at 0.85 GHz

DSA (dB)

-0.02

-0.01

0.01

0.02

-40qC

25qC

105qC

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz,

channel with the median variation over DSA setting at 25°C

Differential Phase Error = PhaseOUT(DSA Setting – 1) –

PhaseOUT(DSA Setting) + 1

Figure 6-294. TX Calibrated Differential Phase Error vs DSA

Setting and Temperature at 0.85 GHz

DSA (dB)

-0.02

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2

-40qC

25qC

105qC

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Integrated Phase Error = PhaseOUT(DSA Setting) –

PhaseOUT(DSA Setting = 0)

Figure 6-295. TX Uncalibrated Integrated Phase Error vs DSA

Setting and Temperature at 0.85 GHz

DSA (dB)

-0.3

-0.25

-0.2

-0.15

-0.1

-0.05

-40qC

25qC

105qC

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Integrated Phase Error = PhaseOUT(DSA Setting) –

PhaseOUT(DSA Setting = 0)

Figure 6-296. TX Calibrated Integrated Phase Error vs DSA

Setting and Temperature at 0.85 GHz

www.ti.com

AFE7900

SBASA44A – AUGUST 2021 – REVISED MARCH 2022

Submit Document Feedback

Product Folder Links: AFE7900

AFE7900IALK Datasheet(PDF) 87 Page - Texas Instruments

AFE7900IALK Datasheet(HTML) 87 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL