LP5891 datasheet(32/74 Pages) TI

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Figure 7-27. LP5891 Memory-unit Structure

7.6.1.3 Write a Frame Data into Memory Bank

After power on, the LP5891 internal flag BANK_SEL, and counters LINE_COUNT, CHANNEL_COUNT, are all

initialized to 0. Thus, the memory unit of channel R0/G0/B0, locating in line 0 of BANK A, is selected to restore

the data transimitted the first time after VSYNC command.

When the first WRTGS command is received, all the data in the common shift register is latched into the

memory unit of channel R0/G0/B0, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and

LINE_COUNT stays the same. Thus, the memory unit of channel R1/G1/B1, locating in line 0 of BANK A, is

selected to restore the data transimitted the second time after VSYNC command.

When the second WRTGS command is received, all the data in the common shift register is latched into the

memory unit of channel R1/G1/B1, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and

LINE_COUNT stays the same. Thus, the memory unit of channel R2/G2/B2, locating in line 0 of BANK A, is

selected to restore the data transimitted the third time after VSYNC command.

Repeat the grayscale-data-write operation until the 16th WRTGS command is received. Then

CHANNEL_COUNT is reset to 0 and LINE_COUNT increases by 1. Thus, the memory unit of channel

R0/G0/B0, locating in line 1 of BANK A, is selected to restore the data transimitted the 17th time after VSYNC

command.

LP5891

SLDS269A – MARCH 2022 – REVISED MAY 2022

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LP5891 Datasheet(PDF) 32 Page - Texas Instruments