LP5891 datasheet(17/74 Pages) TI

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to 0 to disable the bypass switch (enable the ½ divider), while the GCLK frequency is higher than 80 MHz, the

GCLK_MOD is set to 1 to enable the bypass switch (disable the ½ divider).

1/2

SCLK

GCLK_MUL

GCLK_MOD

GCLK

Figure 7-6. Frequency Multiplier Block Diagram

7.3.4 Line Transitioning Sequence

The LP5891 defines a timing sequence of scan line transition, shown as Figure 7-7. T_SW is the total

transitioning time. T_SW is broken up into four intervals: T0 is the time interval between the end of PWM time

in current segment and the beginning of channel pre-discharge, T1 is the time interval between the beginning

of the channel pre-discharge and the beginning of current line OFF, T2 is the time interval that the beginning of

current line OFF and the beginning of next line ON, T3 is the time interval of the beginning of next line ON and

the beginning of PWM time in next segment.

Figure 7-7. Line Transitioning Sequence

The line switch time T_SW equals to T0 + T1 + T2 + T3. T_SW can be configured by the LINE_SWT (see FC1

Table 7-4 is the relation between LINE_SWT bits and the line switch time (GCLK numbers) with different internal

GCLK frequency.

Table 7-4. Line Switch Time

LINE_SW

GCLK

Numbers

T_SW (us, 40

MHZ GCLK)

T_SW (us, 60 MHZ

GCLK)

T_SW (us, 100 MHZ

GCLK)

T_SW (us, 120 MHZ

GCLK)

T_SW (us, 160 MHZ

GCLK)

0000b

1.125

0.7515

0.45

0.3735

0.2835

0001b

1.5

1.002

0.6

0.498

0.378

0010b

2.25

1.503

0.9

0.747

0.567

0011b

120

2.004

1.2

0.996

0.756

0100b

150

3.75

2.505

1.5

1.245

0.945

0101b

180

4.5

3.006

1.8

1.494

1.134

0110b

210

5.25

3.507

2.1

1.743

1.323

0111b

240

4.008

2.4

1.992

1.512

1000b

270

6.75

4.509

2.7

2.241

1.701

1001b

300

7.5

5.01

2.49

1.89

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LP5891

SLDS269A – MARCH 2022 – REVISED MAY 2022

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