LP5891 datasheet(9/74 Pages) TI

9 / 74 page

:%;=N

+:0 + +:1 + ® + +:14 + +:15

F Ideal Output Current

Ideal Output Current

O×100

Ideal current is calculated by the following equation:

+&'#.

_4(KN ) KN $) =

+4'(

× )#+0($%) ×

1 + %%_4(KN %%_) KN %%_$)

256

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(3)

Line regulation is calculated by the following equation. (X = R or G or B, n = 0-15):

∆ %V = IXn at VLED=5.5 V − IXn at VLED=2.5 V

IXn at VLED=2.5 V

× 100

5.5 V−2.5 V

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(4)

Load regulation is calculated by the following equation. (X = R or G or B, n = 0-15):

∆ %V = IXn at VXn=1 V − IXn at VXn=3 V

IXn at VXn=3 V

× 100

3 V−1 V

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6.6 Timing Requirements

At VCC = VR = 2.8 V, VG/B = 3.8 V, TA = –40°C to +85°C for LP5891RRFR and LP5891ZXLR while TA = –40°C to +125°C for

LP5891MRRFR; Typical values are at TA = 25°C (unless otherwise specified)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fSCLK

Clock frequency (SCLK)

MHz

tw(H0)

High level pulse duration (SCLK)

tw(L0)

Low level pulse duration (SCLK)

tsu(0)

Set-up time

SIN to SCLK↑

th(0)

Hold time

SCLK↑ to SIN↑↓

6.7 Switching Characteristics

At VCC = VR = 2.8 V, VG/B = 3.8 V, TA = –40°C to +85°C for LP5891RRFR and LP5891ZXLR while TA = –40°C to +125°C for

LP5891MRRFR; Typical values are at TA = 25°C (unless otherwise specified)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Rise time (SOUT)

VCC = 3.3 V, CSOUT = 30 pF

Fall time (SOUT)

VCC = 3.3 V, CSOUT = 30 pF

tpd(0)

Propagation delay

SCLK↑ to SOUT↑↓, full temperature,

CSOUT = 30 pF

3.5

14.2

(1). Input pulse rise and fall time is 2 ns typically.

Figure 6-1. Timing and Switching Diagram

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LP5891

SLDS269A – MARCH 2022 – REVISED MAY 2022

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