Tripath Technology, Inc. – Preliminary Technical Information

11

TCD6000 – Rev. 1.0/09.04

or writing. When the last bit is HIGH, the master is reading from a register on the slave. When the last bit is

LOW, the master is writing to a register on the slave.

ADDR2

ADDR1

TCD6000 write

address

TCD6000 read

address

0

0

80h

81h

0

1

82h

83h

1

0

84h

85h

1

1

86h

87h

The I

reading and writing. Both SCK and SDA are bidirectional lines connected to VD33 via a pull-up resistor.

When the bus is free both lines are HIGH.

The SCK clock frequency is typically less than 400 kHz. Data is transmitted serially in groups of 8 bits,

followed by an acknowledge bit. The data on the SDA line is expected to be stable while SCK is HIGH.

start

stop

A7

A6

A5

A4

A3

A2

A1

R/W

D7

D6

D5

D4

D3

D2

D1

D0

ACK

ACK

SCK

SDA

A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH.

After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted

after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the

master is receiving data from the slave or transmitting data to the slave. When an address is sent, each

device in the system compares the first seven bits after a start condition with its address. If they match, the

device considers itself addressed by the master. Data transfer with acknowledge is obligatory. The

transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data

line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver

which has been addressed is obliged to generate an acknowledge after each byte of data has been

received. The receiver can hold the SCK line LOW after an acknowledge to force the transmitter to wait until

the receiver is ready to accept another byte.

When addressed as a slave, the following protocol must be adhered to, once a slave acknowledge has been

returned, an 8-bit sub-address will be transmitted. If the LSB of the slave address was ‘1’, a repeated

START condition will have to be issued after the address byte; if the LSB is ‘0’ the master will transmit to the

slave with direction unchanged.

When the master writes data to the slave, the following events occur:

0.

SDA and SCK are both HIGH.

1.

A start condition is generated when the master pulls SDA LOW.

2.

The master begins toggling SCK and transmits the slave’s device address on SDA with a 0 in

the LSB (ex. 80h).

3.

On the ninth SCK pulse, the master releases SDA and the slave acknowledges by pulling SDA

LOW.

4.

The slave holds SCK low until it is ready to receive the next byte.

5.

The slave releases SCK and the master begins toggling SCK and transmits the control register

address on SDA.

6.

On the ninth SCK pulse, the master releases SDA and the slave acknowledges by pulling SDA

LOW.

7.

The slave holds SCK low until it is ready to receive the next byte.

8.

The slave releases SCK and the master begins toggling SCK and transmits the data byte on

SDA.

9.

On the ninth SCK pulse, the master releases SDA and the slave acknowledges by pulling SDA

LOW.

10. The slave holds SCK low until it is ready to receive the next byte.

11. To transmit additional data bytes, repeat steps 8 through 10.

12. A stop condition is generated when SCK is released and SDA goes HIGH while SCK is still

high.