AM2434 datasheet(7/282 Pages) TI

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4 Revision History

Changes from August 30, 2022 to September 21, 2022 (from Revision D (August 2022) to

Revision E (September 2022))

Page

• Global: Changed the document product status from "Production Data" to "ProdMix" to include both

"Production Data" and "Advance Information" . Currently, only the ALV mechanical package is fully-qualified

and has Production Data orderables. The ALX mechanical package is not fully-qualified and is still "Advance

Information" plus, identified as "Preview", where applicable.............................................................................. 1

• (Applications): Added the linked Condition-Monitoring Gateway bullet.............................................................. 3

• (Pin Attributes Header List): Added PULL UP/DOWN resister note................................................................. 18

• (Pin Connectivity Requirements): Deleted pin J15 from the row associated with VDDS_MMC0................... 110

• (ESD Ratings): Replaced TBD values with tested values...............................................................................118

• (High-Frequency Oscillator (HFOSC) Electrical Characteristics): Defined maximum Input Leakage Current

value............................................................................................................................................................... 124

• (ADC12B Electrical Characteristics): Changed the maximum input leakage of General Purpose Input Mode

from 2μA to 10μA............................................................................................................................................127

• Included "Recommended Clock, System, and Control Signal Transition Behavior" section and associated

details............................................................................................................................................................. 150

• (Clock Specifications): Included an new/updated section titled "Recommended System Precautions for Clock

and Control Signal Transitions"...................................................................................................................... 150

• (OSPI0 Timing Requirements – PHY SDR Mode): Updated all setup and hold values..................................217

Changes from March 15, 2022 to August 29, 2022 (from Revision C (March 2022) to Revision D

(August 2022))

Page

• Removed support claims for USB 3.1 SuperSpeed Host Mode......................................................................... 1

• (Features; Functional Safety-compliant): Updated the "Hardware integrity up to SIL 2 targeted" bullet to

remove "for MCU domain" since the new compliance target includes both MCU and MAIN domains...............1

• (Description): Updated/Changed the "Device Information" table title to now "Package Information"................. 4

• General text cleanup for readability and reference. Including two footnotes that were filtered weird. This topic

is only used by AM243x......................................................................................................................................5

• (Functional Block Diagram): Clarified FSITX and FSIRX instance count........................................................... 5

• (Functional Block Diagram): Added note regarding AM243x SW Build Sheet................................................... 5

• (Functional Block Diagram): Updated PRU_ICSSG block to include ECAP and PWM functionality..................5

• (Functional Block Diagram): Updated 2-Port Gb Ethernet to 3-Port Gb Ethernet and added descriptive

footnote...............................................................................................................................................................5

• (Device Comparison): Merged common rows. Removed Speed Grade K option from AM2431_ALV. Added

Speed Grade K option to AM2432_ALX and AM2431_ALX.............................................................................13

• (Device Comparison): Added a clarification Note that the device feature codes are defined in the Device

Naming Convention section..............................................................................................................................13

• (Related Products): Added Sitara™ Microcontrollers and related links............................................................15

• (ALV FCBGA-N441 Pin Diagram): Changed definition of pin J15 from VDDS_MMC0 (MMC0 PHY IO supply)

to ADC0_REFP (ADC0 Positive Voltage Reference)....................................................................................... 16

• (ALV FCBGA-N441 Pin Diagram): Changed definition of pin J16 from VSS (Ground) to ADC0_REFN (ADC0

Negative Voltage Reference)............................................................................................................................16

• (Pin Attributes Header List): Added "OD" signal type and direction................................................................. 18

• (EQEP Signal Descriptions): Added EQEP debounce footnotes......................................................................21

• (Pin Attributes - ALV Pin J16): VSS (Ground) replaced with ADC0_REFN (ADC0 Negative Voltage

Reference)........................................................................................................................................................ 21

• (Pin Attributes - Pin F18): Removed the "PU/PD" value from the "PULL UP/DOWN TYPE" column since this

pin does not have internal pulls........................................................................................................................ 21

• (GPIO Signal Descriptions): Added note regarding GPIO signals implemented with I2C OD FS voltage buffers

and updated associated signal types from IO to IOD....................................................................................... 21

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AM2434, AM2432, AM2431

SPRSP65E – APRIL 2021 – REVISED SEPTEMBER 2022

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