STA1295 datasheet(96/109 Pages) STMICROELECTRONICS

96 / 109 page

Electrical characteristics

STA1295, STA1275

96/109

DS12586 Rev 5

Launching and capturing clock edges are as per standard. This means: in Default Speed

mode, launching occurs on falling clock edges and capturing occurs on rising clock edges.

In High Speed mode and SDR50 mode, launching and capturing both occur on rising clock

edges.

Timings are provided taking the active edge at SoC side as reference.

Table 55. Normal Speed (JEDEC); Default Speed (SD); UHS- I SDR12 (SD)

Type

Symbol

Min Max Unit Load

Notes

Clock

CLK freq

—

MHz 25 pF

IP can run up to 26 MHz. For SD modes, setting

of 24 MHz is recommended to meet typical

external component limitations (25 MHz).

CLK period

38.4

—

25 pF

—

CLK duty cycle

—

Input

TIS

—

7 ns in case internal clocking mode is used (no

feedback clock).

TIH

—

Output Todly

5.5

25 pF

Output hold time is taken care of by capturing

on opposite clock edge.

Table 56. High Speed SDR (JEDEC); High Speed (SD); UHS- I SDR25 (SD)

Type

Symbol

Min Max Unit Load

Notes

Clock

CLK freq

—

MHz 25 pF

IP can run up to 52 MHz. For SD modes, setting

of 48 MHz is recommended to meet typical

external component limitations (50 MHz).

CLK period

19.2

—

25 pF

—

CLK duty cycle

—

Input

TIS

—

TIH

—

Output Todly

5.5

25 pF

Table 57. HS200 (JEDEC); UHS- I UHS50: SDR50 (SD)

Type

Symbol

Min Max Unit Load

Notes

Clock

CLK freq

—

104 MHz 25 pF

IP can run up to 104 MHz. Setting of 96 MHz is

recommended to meet typical external

component limitations (100 MHz).

CLK period

9.6

—

25 pF

—

CLK duty cycle

—

Input

TIS

—

TIH

—

Output Todly

5.2

25 pF

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