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STA1295 Datasheet(PDF) 101 Page - STMicroelectronics |
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STA1295 Datasheet(HTML) 101 Page - STMicroelectronics |
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101 / 109 page  DS12586 Rev 5 101/109 STA1295, STA1275 Electrical characteristics 106 4.14.8 MSP (I2S) interface timing The following tables provide the timings for MSP interface. Opposite edge data capture protocol should be used for both master and slave modes. All timings are given with regards to the active clock edge (capturing edge for input and launching edge for output). Table 69. RGMII mode Type Symbol Min Max Unit Load Notes Clock CLK freq — 50 MHz 10 pF — CLK period 20 — ns 10 pF CLK duty cycle 40 60 % — Input TIS 2 — ns — TIH 2 — ns — Output Todly 2 10 ns 10 pF Table 70. MSP2 - Master Type Symbol Min Max Unit Load Notes Clock CLK freq — 12.5 MHz 25 pF — CLK period 80 — ns 25 pF CLK duty cycle 40 60 % — Input TIS 18 — ns — TIH 0 — ns — Output Todly -0.5 2 ns 25 pF Table 71. MSP0 - Master Type Symbol Min Max Unit Load Notes Clock CLK freq — 12.5 MHz 25 pF — CLK period 80 — ns 25 pF CLK duty cycle 40 60 % — Input TIS 12 — ns — TIH 0 — ns — Output Todly -0.5 2 ns 25 pF |
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