CS43131 datasheet(60/156 Pages) CIRRUS

60 / 156 page

DS1155F1

CS43131

4.13 Control Port Operation

Each byte transferred on the I2C bus is separated by an acknowledge (ACK) bit. The CS43131 acknowledges each input

byte read from the host, and the host must acknowledge each byte transmitted from the CS43131.

For write operations, the data bytes following the MAP byte are written to the CS43131 register addresses pointed to by

the last received MAP address, plus however many autoincrements have occurred. Fig. 4-32 shows a write pattern with

autoincrementing.

Figure 4-32. Control Port Timing, I2C Writes with Autoincrement (8-bit Data Access)

For read operations, the contents of the register pointed to by the last received MAP address (plus however many

autoincrements have occurred if INCR was previously set) are output in the next byte. Fig. 4-33 shows a read pattern

following the write pattern in Fig. 4-32. Notice how read addresses are based on the MAP bytes from Fig. 4-32.

Figure 4-33. Control Port Timing, I2C Reads with Autoincrement (8-Bit Data Access)

INCR

Setting this bit allows the MAP address to autoincrement. The MAP address automatically increments every SIZE + 1 bytes

accessed consecutively.

0 Disabled

1 Enabled

Table 4-13. I2C Control-Byte Format (Cont.)

Bit

Name

Description

SCL

CHIP ADDRESS

(WRITE)

MAP BYTE

High (23:16)

START

STOP

ACK

SDA

Source

Master

Pull-up

Slave

Pull-up

ACK

Slave

6 7 8

17 18

7 6 5 4 3 2 1 0

ACK

MAP BYTE

Mid (15:8)

MAP BYTE

Low (7:0)

ACK

CONTROL

BYTE

7 6 5 4 3 2 1 0

37 38

Empty

26 27

39 40 41 42 43 44

DATA

BYTE 1

DATA

BYTE N

Master

Slave

MAP

ADDRESS

MAP

ADDRESS

+ (N–1)

ACK

Addr = 01100

SCL

CHIP ADDRESS

(READ)

START

SDA

Source

Master

Pull-up

Slave

Pull-up

ACK

6 7 8

7 6 5 4 3 2 1 0

ACK

NACK

DATA

BYTE 1

DATA

BYTE N

Slave

STOP

MAP

ADDRESS

MAP

ADDRESS

+ (N–1 )

Addr = 01100

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