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CS43131 Datasheet(PDF) 74 Page - Cirrus Logic |
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CS43131 Datasheet(HTML) 74 Page - Cirrus Logic |
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74 / 156 page  74 DS1155F1 CS43131 5.13 Example Sequences 5.13 Example Sequences This section provides recommended instruction sequences for standard CS43131 operations. 5.13.1 Power-up Sequence to I2S Playback In Ex. 5-7, a 22.5792-MHz crystal is used, ASP is set to I2S master at 44.1 kHz, and full-scale output is 1.732 Vrms. Example 5-7. Startup to I2S Playback STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION 1 Apply all relevant power supplies, then assert RESET. 2 Wait for 1.5 ms. 3 Configure XTAL driver 4 Configure XTAL bias current strength (assuming River Crystal at 22.5792 MHz) Crystal Setting. 0x20052 0x04 Reserved XTAL_IBIAS 0000 0 100 Bias current set to 12.5 µA 5 Read Interrupt Status 1 register (0xF0000) to clear any pending interrupts. 6 Enable XTAL interrupts Interrupt Mask 1. 0xF0010 0xE7 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK 1 1 1 0 0 1 1 1 Enable XTAL_READY interrupt Enable XTAL_ERROR interrupt 7 Start XTAL Power Down Control. 0x20000 0xF6 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved 1 1 1 1 0 1 1 0 Power up XTAL driver 8 Configure ASP interface. Sample rate set to 44.1 kHz. ASP is clock master. 9 Set ASP sample rate Serial Port Sample Rate. 0x1000B 0x01 Reserved ASP_SPRATE 0000 0001 Set sample rate to 44.1 kHz 10 Set ASP sample bit size. XSP is don't care Serial Port Sample Bit Size. 0x1000C 0x04 Reserved XSP_SPSIZE ASP_SPSIZE 0000 01 00 XSP sample bit size set to 24 bits ASP sample bit size set to 32 bits 11 Set ASP numerator ASP Numerator 1. 0x40010 0x01 ASP_N_LSB 0x01 LSB of ASP sample rate fractional divide numerator ASP Numerator 2. 0x40011 0x00 ASP_N_MSB 0x00 MSB of ASP sample rate fractional divide numerator 12 Set ASP denominator ASP Denominator 1. 0x40012 0x08 ASP_M_LSB 0x08 LSB of ASP sample rate fractional divide denominator ASP Denominator 2. 0x40013 0x00 ASP_M_MSB 0x00 MSB of ASP sample rate fractional divide denominator 13 Set ASP LRCK high time ASP LRCK High Time 1. 0x40014 0x1F ASP_LCHI_LSB 0x1F LSB of ASP LRCK high time duration ASP LRCK High Time 2. 0x40015 0x00 ASP_LCHI_MSB 0x00 MSB of ASP LRCK high time duration 14 Set ASP LRCK period ASP LRCK Period 1. 0x40016 0x3F ASP_LCPR_LSB 0x3F LSB of ASP LRCK period ASP LRCK Period 2. 0x40017 0x00 ASP_LCPR_MSB 0x00 MSB of ASP LRCK period 15 Configure ASP clock ASP Clock Configuration. 0x40018 0x1C Reserved ASP_M/SB ASP_SCPOL_OUT ASP_SCPOL_IN ASP_LCPOL_OUT ASP_LCPOL_IN 000 1 1 1 0 0 Set ASP port to be master Configure clock polarity for I2S input |
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