CS43131 datasheet(29/156 Pages) CIRRUS

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DS1155F1

CS43131

4.1 Overview

4.1.5

Audio Interfaces and Supported Formats

There are two serial input ports on the CS43131, the audio serial port (ASP) and the auxiliary serial port (XSP). The ASP

on the CS43131 supports I2S, TDM, and DoP (DSD over PCM) formats up to a 384-kHz sample rate. The XSP on the

CS43131 supports the DoP format up to a 352.8-kHz sample rate.

The CS43131 also has a dedicated DSD interface to support up to a 256•Fs DSD stream. The DSD interface shares pins

with the XSP.

4.1.6

System Clocking

The CS43131 internal MCLK can be sourced from three options:

• Direct MCLK/crystal mode. The internal MCLK is provided through XTI/MCLK pin directly or generated by crystal

oscillator.

• PLL mode. A PLL reference CLK is provided by externally through XTI/MCLK. The PLL is configured, and output is

used as the internal MCLK.

• RCO mode. An internal RCO is used as the internal MCLK. Note that HPIN input path is the only supported audio

playback feature in this mode for optimized power consumption. This mode can also support HP detection and I2C

communication. DAC playback and headphone impedance measurement functions are not supported.

The clock output is provided for audio applications that require high quality audio rate system clock. This clock output can

be sourced from the following two options:

• The clock generated by the CS43131 crystal oscillator.

• Output of the internal Fractional-N PLL that refers to MCLK input. See Section 4.7.1 for supported frequencies.

The internal MCLK is used to generate serial port clocks. See Table 4-6 for supported LRCK combinations.

4.1.7

System Interrupts

The CS43131 includes an open-drain interrupt output (INT pin). Interrupt mask registers control whether an event

associated with an interrupt status/mask bit pair triggers the assertion of INT. All types of interrupt are described in

Section 4.11.

4.1.8

System Reset

The CS43131 offers two types of reset options:

• Asserting RESET. If RESET is asserted, all registers and state machines are immediately set to their default values/

states. No operation can begin until RESET is deasserted. Before normal operation can begin, RESET must be

asserted at least once after the VP supply is first brought up.

• Power-on reset (POR). If the VD supply is lower than the POR threshold specified in Table 3-18, all registers and

state machines are set to their default values/states. The POR releases the reset when the VD supply goes above

the POR threshold. When the VD supply is turned on, the VL and VA supplies must also be turned on at the same

time.

4.1.9

Power Down

The CS43131 has a register to power down individual components on the chip. Before any change can be applied to an

individual component (except PLL), the block must be powered down first. For the PLL, changes can be applied after PLL_

START is cleared.

The PDN_HP bit is responsible for enabling or disabling the signal chain playback operation. Setting PDN_HP disables

signal chain playback operation. All the necessary components for playback operation need to be powered up and

configured properly before PDN_HP is cleared. PDN_HP needs to be set before making any changes to the playback

signal chain setup, except the following functions:

• Volume and mute related functions

• PCM filter settings (see Section 7.5.2)

CS43131 Datasheet(PDF) 29 Page - Cirrus Logic

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